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PIC24FJ64GA 数据表(PDF) 13 Page - Microchip Technology |
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PIC24FJ64GA 数据表(HTML) 13 Page - Microchip Technology |
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13 / 52 page  © 2008 Microchip Technology Inc. DS39768D-page 13 PIC24FJXXXGA0XX 3.2.1 SIX SERIAL INSTRUCTION EXECUTION The SIX control code allows execution of the PIC24FJXXXGA0XX family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles, as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGC clock cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-2). Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up, resulting in a 9-bit SIX command instead of the normal 4-bit SIX command. After the forced SIX is clocked in, ICSP operation resumes as normal. That is, the next 24 clock cycles load the first instruction word to the CPU. FIGURE 3-2: SIX SERIAL EXECUTION 3.2.1.1 Differences Between Execution of SIX and Normal Instructions There are some differences between executing instruc- tions normally and using the SIX ICSP command. As a result, the code examples in this specification may not match those for performing the same functions during normal device operation. The important differences are: • Two-word instructions require two SIX operations to clock in all the necessary data. Examples of two-word instructions are GOTO and CALL . • Two-cycle instructions require two SIX operations. The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation – which should shift in a NOP to avoid losing data – provides the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are table read and table write instructions. • The CPU does not automatically stall to account for pipeline changes. A CPU stall occurs when an instruction modifies a register that is used for Indirect Addressing by the following instruction. During normal operation, the CPU automatically will force a NOP while the new data is read. When using ICSP, there is no automatic stall, so any indirect references to a recently modified register should be preceded by a NOP. For example, the instructions, mov #0x0,W0 and mov [W0],W1 , must have a NOP inserted between them. If a two-cycle instruction modifies a register that is used indirectly, it will require two following NOPs: one to execute the second half of the instruction and a second to stall the CPU to correct the pipeline. Instructions such as tblwtl [W0++],[W1] should be followed by two NOPs. • The device Program Counter (PC) continues to automatically increment during ICSP instruction execution, even though the Flash memory is not being used. As a result, the PC may be incremented to point to invalid memory locations. Invalid memory spaces include unimplemented Flash addresses and the vector space (locations 0x0 to 0x1FF). If the PC points to these locations, the device will reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method to accomplish this is to perform a GOTO 0x200 . Note: To account for this forced NOP, all example code in this specification begin with a NOP to ensure that no data is lost. P4 23 1 2 3 23 24 1 2 3 4 P1 PGCx P4A PGDx 24-Bit Instruction Fetch Execute PC – 1, 16 00 0 0 Fetch SIX 45 6 7 8 18 19 20 21 22 17 LSB X X X X X X X X X X X X X X MSB PGDx = Input P2 P3 P1B P1A 78 9 00 0 0 00 0 Only for Program Memory Entry Control Code 4 5 Execute 24-Bit Instruction, Fetch Next Control Code 00 |
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