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PIC24FJ64GA 数据表(PDF) 34 Page - Microchip Technology |
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PIC24FJ64GA 数据表(HTML) 34 Page - Microchip Technology |
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34 / 52 page  PIC24FJXXXGA0XX DS39768D-page 34 © 2008 Microchip Technology Inc. 5.0 THE PROGRAMMING EXECUTIVE 5.1 Programming Executive Communication The programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave. All communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the programming executive. In turn, the programming executive only sends one response to the programmer after receiving and processing a command. The programming executive command set is described in Section 5.2 “Programming Executive Commands”. The response set is described in Section 5.3 “Programming Executive Responses”. 5.1.1 COMMUNICATION INTERFACE AND PROTOCOL The Enhanced ICSP interface is a 2-wire SPI, implemented using the PGCx and PGDx pins. The PGCx pin is used as a clock input pin and the clock source must be provided by the programmer. The PGDx pin is used for sending command data to, and receiving response data from, the programming executive. Data transmits to the device must change on the rising edge and hold on the falling edge. Data receives from the device must change on the falling edge and hold on the rising edge. All data transmissions are sent to the Most Significant bit (MSb) first, using 16-bit mode (see Figure 5-1). FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE FIGURE 5-2: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE Since a 2-wire SPI is used, and data transmissions are half duplex, a simple protocol is used to control the direction of PGDx. When the programmer completes a command transmission, it releases the PGDx line and allows the programming executive to drive this line high. The programming executive keeps the PGDx line high to indicate that it is processing the command. After the programming executive has processed the command, it brings PGDx low for 15 μsec to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response 23 μsec after PGDx is brought low, and it must provide the necessary amount of clock pulses to receive the entire response from the programming executive. After the entire response is clocked out, the program- mer should terminate the clock on PGCx until it is time to send another command to the programming executive. This protocol is shown in Figure 5-3. 5.1.2 SPI RATE In Enhanced ICSP mode, the PIC24FJXXXGA0XX family devices operate from the internal Fast RC oscil- lator (FRCDIV), which has a nominal frequency of 8 MHz. This oscillator frequency yields an effective system clock frequency of 4 MHz. To ensure that the programmer does not clock too fast, it is recommended that a 4 MHz clock be provided by the programmer. 5.1.3 TIME-OUTS The programming executive uses no Watchdog Timer or time-out for transmitting responses to the program- mer. If the programmer does not follow the flow control mechanism using PGCx, as described in Section 5.1.1 “Communication Interface and Protocol”, it is possible that the programming executive will behave unexpectedly while trying to send a response to the programmer. Since the programming executive has no time-out, it is imperative that the programmer correctly follow the described communication protocol. As a safety measure, the programmer should use the command time-outs identified in Table 5-1. If the command time-out expires, the programmer should reset the programming executive and start programming the device again. PGCx PGDx 12 3 11 13 15 16 14 12 LSb 14 13 12 11 45 6 MSb 1 2 3 ... 4 5 P2 P3 P1 P1B P1A PGCx PGDx 12 3 11 13 15 16 14 12 LSb 14 13 12 11 45 6 MSb 1 2 3 ... 4 5 P2 P3 P1 P1B P1A |
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