 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
PIC24FJ64GA 数据表(PDF) 16 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC24FJ64GA 数据表(HTML) 16 Page - Microchip Technology |
|
|
16 / 52 page  PIC24FJXXXGA0XX DS39768D-page 16 © 2008 Microchip Technology Inc. 3.4 Flash Memory Programming in ICSP Mode 3.4.1 PROGRAMMING OPERATIONS Flash memory write and erase operations are controlled by the NVMCON register. Programming is performed by setting NVMCON to select the type of erase operation (Table 3-2) or write operation (Table 3-3) and initiating the programming by setting the WR control bit (NVMCON<15>). In ICSP mode, all programming operations are self-timed. There is an internal delay between the user setting the WR control bit and the automatic clearing of the WR control bit when the programming operation is complete. Please refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for information about the delays associated with various programming operations. TABLE 3-2: NVMCON ERASE OPERATIONS TABLE 3-3: NVMCON WRITE OPERATIONS 3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE The WR bit (NVMCON<15>) is used to start an erase or write cycle. Setting the WR bit initiates the programming cycle. All erase and write cycles are self-timed. The WR bit should be polled to determine if the erase or write cycle has been completed. Starting a programming cycle is performed as follows: 3.5 Erasing Program Memory The procedure for erasing program memory (all of code memory, data memory, executive memory and code-protect bits) consists of setting NVMCON to 404Fh and executing the programming cycle. A Chip Erase can erase all of user memory or all of both the user and configuration memory. A table write instruction should be executed prior to performing the Chip Erase to select which sections are erased. When this table write instruction is executed: • If the TBLPAG register points to user space (is less than 0x80), the Chip Erase will erase only user memory. • If TBLPAG points to configuration space (is greater than or equal to 0x80), the Chip Erase will erase both user and configuration memory. If configuration memory is erased, the internal oscillator Calibration Word, located at 0x807FE, will be erased. This location should be stored prior to performing a whole Chip Erase and restored afterward to prevent internal oscillators from becoming uncalibrated. Figure 3-5 shows the ICSP programming process for performing a Chip Erase. This process includes the ICSP command code, which must be transmitted (for each instruction), Least Significant bit first, using the PGCx and PGDx pins (see Figure 3-2). FIGURE 3-5: CHIP ERASE FLOW NVMCON Value Erase Operation 404Fh Erase all code memory, executive memory and Configuration registers (does not erase Unit ID or Device ID registers). 4042h Erase a page of code memory or executive memory. NVMCON Value Write Operation 4003h Write a Configuration Word register. 4001h Program 1 row (64 instruction words) of code memory or executive memory. BSET NVMCON, #WR Note: Program memory must be erased before writing any data to program memory. Start Done Set the WR bit to Initiate Erase Write 404Fh to NVMCON SFR Delay P11 + P10 Time |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
