PSD813F2 datasheet(87/128 Pages) STMICROELECTRONICS

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PSD8XXFX

Programming in-circuit using the JTAG serial interface

Doc ID 7833 Rev 7

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Programming in-circuit using the JTAG serial

interface

The JTAG Serial Interface block can be enabled on port C (see Table 35). All memory blocks

(primary and secondary Flash memory), PLD logic, and PSD Configuration register bits may

be programmed through the JTAG Serial Interface block. A blank device can be mounted on

a printed circuit board and programmed using JTAG.

The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional

signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and

Erase cycles.

Note:

By default, on a blank PSD (as shipped from the factory or after erasure), four pins on port C

are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.

See Application Note AN1153 for more details on JTAG in-system programming (ISP).

19.1

Standard JTAG signals

The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three

different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are

inputs, waiting for a JTAG serial command from an external JTAG controller device (such as

FlashLINK or Automated Test Equipment). When the enabling command is received, TDO

becomes an output and the JTAG channel is fully functional inside the PSD. The same

command that enables the JTAG channel may optionally enable the two additional JTAG

signals, TSTAT and TERR.

The following symbolic logic equation specifies the conditions enabling the four basic JTAG

signals (TMS, TCK, TDI, and TDO) on their respective port C pins. For purposes of

discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are

enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O.

JTAG_ON = PSDsoft_enabled +

/* An NVM configuration bit inside the PSD is set by the designer

in the PSDsoft Express Configuration utility. This dedicates the

pins for JTAG at all times (compliant with IEEE 1149.1 */

Microcontroller_enabled +

/* The microcontroller can set a bit at run-time by writing to the

PSD register, JTAG Enable. This register is located at address CSIOP

+ offset C7h. Setting the JTAG_ENABLE bit in this register will

enable the pins for JTAG use. This bit is cleared by a PSD reset or

the microcontroller. See Table 36 for bit definition. */

PSD_product_term_enabled;

/* A dedicated product term (PT) inside the PSD can be used to

enable the JTAG pins. This PT has the reserved name JTAGSEL. Once

defined as a node in PSDabel, the designer can write an equation for

JTAGSEL. This method is used when the port C JTAG pins are

multiplexed with other I/O signals. It is recommended to logically

tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when

multiplexing JTAG signals. See Application Note 1153 for details. */

The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations

if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft Express). However,

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