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PSD813F2 数据表(PDF) 22 Page - STMicroelectronics |
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PSD813F2 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 128 page  PSD architectural overview PSD8XXFX 22/128 Doc ID 7833 Rev 7 The PSD also has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to sleep until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see Section 17: Power management for more details. Table 5. JTAG SIgnals on port C Port C pins JTAG signal PC0 TMS PC1 TCK PC3 TSTAT PC4 TERR PC5 TDI PC6 TDO Table 6. Methods for programming different functional blocks of the PSD Functional block JTAG programming Device programmer IAP Primary Flash memory Yes Yes Yes Secondary Flash memory Yes Yes Yes PLD array (DPLD and CPLD) Yes Yes No PSD configuration Yes Yes No Obsolete Product(s) - Obsolete Product(s) |
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