PSD813F2 datasheet(88/128 Pages) STMICROELECTRONICS

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Programming in-circuit using the JTAG serial interface

PSD8XXFX

88/128

Doc ID 7833 Rev 7

Reset (RESET) will prevent or interrupt JTAG operations if the JTAG enable register is used

to enable the JTAG pins.

The PSD supports JTAG In-System-Configuration (ISC) commands, but not Boundary

Scan. The PSDsoft Express software tool and FlashLINK JTAG programming cable

implement the JTAG In-System-Configuration (ISC) commands. A definition of these JTAG

In-System-Configuration (ISC) commands and sequences is defined in a supplemental

document available from ST. This document is needed only as a reference for designers

who use a FlashLINK to program their PSD.

19.2

JTAG extensions

TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command

received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to

speed Program and Erase cycles by indicating status on PSD signals instead of having to

scan the status out serially using the standard JTAG channel. See Application Note

AN1153.

TERR indicates if an error has occurred when erasing a sector or programming a byte in

Flash memory. This signal goes low (active) when an Error condition occurs, and stays low

until an “ISC_CLEAR” command is executed or a chip Reset (RESET) pulse is received

after an “ISC_DISABLE” command.

TSTAT behaves the same as Ready/Busy described in Section 6.3.1: Ready/Busy (PC3).

TSTAT is high when the PSD device is in READ mode (primary and secondary Flash

memory contents can be read). TSTAT is low when Flash memory program or erase cycles

are in progress, and also when data is being written to the secondary Flash memory.

TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”

command. This facilitates a wired-OR connection of TSTAT signals from multiple PSD

devices and a wired-OR connection of TERR signals from those same devices. This is

useful when several PSD devices are “chained” together in a JTAG environment.

19.3

Security and Flash memory protection

When the security bit is set, the device cannot be read on a device programmer or through

the JTAG port. When using the JTAG port, only a Full Chip Erase command is allowed.

All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part

to a non-secured blank state. The Security bit can be set in PSDsoft Express configuration.

All primary and secondary Flash memory sectors can individually be sector protected

against erasures. The sector protect bits can be set in PSDsoft Express configuration.

Obsolete

Product(s)

- Obsolete

Product(s)

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