PSD813F2 datasheet(47/128 Pages) STMICROELECTRONICS

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PSD8XXFX

PLDS

Doc ID 7833 Rev 7

47/128

PLDS

The PLDs bring programmable logic functionality to the PSD. After specifying the logic for

the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the

device and available upon Power-up.

The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The

PLDs are briefly discussed in the next few paragraphs, and in more detail in Section 14.2:

Decode PLD (DPLD), and Section 14.3: Complex PLD (CPLD). Figure 12 shows the

configuration of the PLDs.

The DPLD performs address decoding for Select signals for internal components, such as

memory, registers, and I/O ports.

The CPLD can be used for logic functions, such as loadable counters and shift registers,

state machines, and encoding and decoding logic. These logic functions can be constructed

using the 16 Output macrocells (OMC), 24 input macrocells (IMC), and the AND Array. The

CPLD can also be used to generate External Chip Select (ECS0-ECS2) signals.

The AND Array is used to form product terms. These product terms are specified using

PSDabel. An input bus consisting of 73 signals is connected to the PLDs. The signals are

shown in Table 15.

14.1

The Turbo Bit in PSD

The PLDs in the PSD can minimize power consumption by switching off when inputs remain

unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of

PMMR0) automatically places the PLDs into standby if no inputs are changing. Turning the

Turbo mode off increases propagation delays while reducing power consumption. See

Section 17: Power management on how to set the Turbo Bit.

Additionally, five bits are available in PMMR2 to block MCU control signals from entering the

PLDs. This reduces power consumption and can be used only when these MCU control

signals are not used in PLD logic equations.

Each of the two PLDs has unique characteristics suited for its applications. They are

described in the following sections.

Table 15.

DPLD and CPLD inputs

Input source

Input name

Number of

signals

MCU address bus(1)

A15-A0

MCU control signals

CNTL2-CNTL0

Reset

RST

Power-down

PDN

Port A input macrocells

PA7-PA0

Port B input macrocells

PB7-PB0

Port C input macrocells

PC7-PC0

Port D inputs

PD2-PD0

Obsolete

Product(s)

- Obsolete

Product(s)

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