PSD813F2 datasheet(30/128 Pages) STMICROELECTRONICS

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Instructions

PSD8XXFX

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Doc ID 7833 Rev 7

Instructions

An instruction consists of a sequence of specific operations. Each received byte is

sequentially decoded by the PSD and not executed as a standard WRITE operation. The

instruction is executed when the correct number of bytes are properly received and the time

between two consecutive bytes is shorter than the timeout period. Some instructions are

structured to include READ operations after the initial WRITE operations.

The instruction must be followed exactly. Any invalid combination of instruction bytes or

timeout between two consecutive bytes while addressing Flash memory resets the device

logic into READ mode (Flash memory is read like a ROM device).

The PSD supports the instructions summarized in Table 10:

Flash memory:

●

Erase memory by chip or sector

●

Suspend or resume sector erase

●

Program a Byte

●

Reset to READ mode

●

Read primary Flash Identifier value

●

Read Sector Protection Status

●

Bypass (on the PSD833F2, PSD834F2, PSD853F2 and PSD854F2)

These instructions are detailed in Table 10. For efficient decoding of the instructions, the first

two bytes of an instruction are the coded cycles and are followed by an instruction byte or

confirmation byte. The coded cycles consist of writing the data AAh to address X555h

during the first cycle and data 55h to address XAAAh during the second cycle. Address

signals A15-A12 are Don’t Care during the instruction WRITE cycles. However, the

appropriate Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) must be selected.

The primary and secondary Flash memories have the same instruction set (except for Read

Primary Flash Identifier). The Sector Select signals determine which Flash memory is to

receive and execute the instruction. The primary Flash memory is selected if any one of

Sector Select (FS0-FS7) is high, and the secondary Flash memory is selected if any one of

Sector Select (CSBOOT0-CSBOOT3) is high.

7.1

Power-up mode

The PSD internal logic is reset upon Power-up to the READ mode. Sector Select (FS0-FS7

and CSBOOT0-CSBOOT3) must be held low, and Write Strobe (WR, CNTL0) high, during

Power-up for maximum security of the data contents and to remove the possibility of a byte

being written on the first edge of Write Strobe (WR, CNTL0). Any WRITE cycle initiation is

locked when VCC is below VLKO.

7.2

READ

Under typical conditions, the MCU may read the primary Flash memory or the secondary

Flash memory using READ operations just as it would a ROM or RAM device. Alternately,

the MCU may use READ operations to obtain status information about a program or erase

Obsolete

Product(s)

- Obsolete

Product(s)

PSD813F2 数据表(PDF) 30 Page - STMicroelectronics

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