PSD813F2 datasheet(107/128 Pages) STMICROELECTRONICS

107 / 128 page

PSD8XXFX

AC/DC parameters

Doc ID 7833 Rev 7

107/128

tTHEH

R/W setup time to Enable

tELTL

R/W hold time After Enable

tAVPV

Address input valid to

Address output delay

(5)

Any input used to select an internal PSD function.

RD timing has the same timing as DS, LDS, and UDS signals.

RD and PSEN have the same timing.

RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

In multiplexed mode, latched addresses generated from ADIO delay to address output on any port.

Table 56.

READ timing (5 V devices) (continued)

Symbol

Parameter

Conditions

-70

-90

-15

Turbo

off

Unit

Min Max Min Max Min

Max

Table 57.

READ timing (3 V devices)

Symbol

Parameter

Conditions

-12

-15

-20

Turbo

off

Unit

Min Max Min

Max

Min Max

tLVLX

ALE or AS pulse width

tAVLX

Address setup time

(1)

910

tLXAX

Address hold time

(1)

912

tAVQV

Address valid to data valid

(1)

120

150

200

+ 20

tSLQV

CS valid to data valid

120

150

200

tRLQV

RD to data valid 8-bit bus

(2)

RD or PSEN to data valid 8-bit bus,

8031, 80251

(3)

tRHQX

RD data hold time

(4)

tRLRH

RD pulse width

tRHQZ

RD to data high-Z

(4)

tEHEL

E pulse width

tTHEH

R/W setup time to enable

tELTL

R/W hold time after enable

tAVPV

Address input valid to

address output delay

(5)

Any input used to select an internal PSD function.

RD timing has the same timing as DS, LDS, and UDS signals.

RD and PSEN have the same timing for 8031.

RD timing has the same timing as DS, LDS, UDS, and PSEN signals.

In multiplexed mode latched address generated from ADIO delay to address output on any port.

Obsolete

Product(s)

- Obsolete

Product(s)

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