AD9524SLASHPCBZ datasheet(3/56 Pages) AD

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Data Sheet

AD9524

Rev. E | Page 3 of 56

REVISION HISTORY

1/14—Rev. D to Rev. E

Change Pin 34 from VDD1.8_OUT[0:3] to VDD1.8_OUT[2:3]

and Pin 42 from NC to VDD1.8_OUT[0:1]................................13

Changes to Writing to the EEPROM Section.................................34

Added Register 0x190.....................................................................40

Changes to EEPROM Buffer Registers.........................................41

Added Table 51 ................................................................................50

2/13—Rev. C to Rev. D

Deleted VDD1.8_PLL2................................................. Throughout

Changes to Data Sheet Title ............................................................1

Added TJ of 115°C, Table 1 ..............................................................4

Changed VDD3_PLL1, Supply Voltage for PLL1 Typical

Parameter from 22 mA to 37 mA and Changed VDD3_PLL1,

Supply Voltage for PLL1 Maximum Parameter from 25.2 mA to

43 mA, Table 2 ...................................................................................4

Changes to Table 3 ............................................................................6

Added PLL1 Characteristics Section and Table 7, Renumbered

Sequentially........................................................................................7

Changes to Table 9 Summary Statement and Changed Differen-

tial Output Voltage Magnitude Unit from mV to V, Table 9 ...........8

Changed Output Timing Skew Between LVPECL, HSTL, and

LVDS Outputs from 164 ps to 234 ps; Added Endnote 1;

Table 10...............................................................................................9

Changes to Pin 5 Description, Table 19 .......................................13

Changed Pin 42 from VDD1.8_PLL2 to NC, Table 19 ..............14

Changes to Figure 24 ......................................................................21

Changes to Multimode Output Drivers Section .........................24

Changes to Clock Distribution Synchronization Section..........25

Changes to Figure 29 and Added Lock Detect Section...............26

Added Reset Modes Section and Power-Down Mode Section ....27

Changes to Pin Descriptions Section and Read Section............31

Added Figure 38; Renumbered Sequentially...............................33

Changes to Register Section Definition Group Section.............36

Changes to Power Dissipation and Thermal Considerations

Section ..............................................................................................38

Changes to Table 31 ........................................................................40

Change to Bit 4 and Bits[1:0] Description, Table 40...................45

Changes to Bit 2 Description, Table 41 and Bits[7:6]

Description, Table 42 ......................................................................46

Changes to Bits[1:0] Description, Table 43..................................47

Changes to Bit 4, Bits [3:2] Descriptions, Table 47.....................48

Changes to Bit 3 Descriptions Table 48........................................49

Changed Bit 6 Name from Status PLL2 Feedback Clock to Status

PLL1 Feedback Clock, Table 54.......................................................52

3/11—Rev. A to Rev. B

Added Table Summary, Table 8.......................................................7

Changes to Table 9 ............................................................................8

Changes to EEPROM Operations Section and Writing to the

EEPROM Section............................................................................32

Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30 ....................37

Changes to Bits[4:3], Table 40 .......................................................43

1/11—Rev. 0 to Rev. A

Changes to General Description Section.......................................1

Changes to Specifications Summary Statement............................4

Changes to Test Conditions/Comments for VDD3_PLL1,

Supply Voltage for PLL1 Parameter, Table 2..................................4

Changes to Typical Configuration and Low Power Typical

Configuration Parameters, Table 3 .................................................5

Changes to Input High Voltage and Input Low Voltage

Parameters; Added Input Threshold Voltage Parameter,

Table 4.................................................................................................5

Changed Differential Output Voltage Swing Parameters to

Differential Output Voltage Magnitude; Changes to Test

Conditions/Comments, Table 8 ......................................................7

Changed Junction Temperature Parameter from 150°C to

115°C, Table 16................................................................................11

Added Figure 14; Renumbered Sequentially...............................15

Changes to Figure 15, Figure 17, and Figure 19; Change to

Caption of Figure 21 .......................................................................16

Added PLL1 Lock Detect Section.................................................19

Changes to VCO Calibration Section...........................................21

Changed Output Mode Section to Multimode Output

Drivers; Changes to Multimode Output Drivers Section..........22

Changes to Figure 29 ......................................................................24

Changes to SPI/I2C Port Selection Section .................................25

Change to SPI Instruction Word (16 Bits) Section.....................29

Added Power Dissipation and Thermal Considerations

Section ..............................................................................................35

Changes to Table 34 to Table 36 and Table 38.............................42

Change to Register 0x0F3, Bit 1 Description, Table 47..............45

Change to Register 0x198, Bits[7:2], Table 50 .............................47

Changes to Table 52 ........................................................................48

Changes to Register 0x230 and Register 0x231, Table 54..........49

7/10—Revision 0: Initial Version

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