AD9524SLASHPCBZ datasheet(11/56 Pages) AD

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Data Sheet

AD9524

Rev. E | Page 11 of 56

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

3.3

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup, tS

CS to SCLK Setup and Hold, tS, tC

CS Minimum Pulse Width High, tPWH

SERIAL CONTROL PORT—I²C MODE

VDD = VDD3_REF, unless otherwise noted.

Table 16.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (WHEN INPUTTING DATA)

Input Logic 1 Voltage

0.7 × VDD

Input Logic 0 Voltage

0.3 × VDD

Input Current with an Input Voltage Between

0.1 × VDD and 0.9 × VDD

−10

+10

µA

Hysteresis of Schmitt Trigger Inputs

0.015 × VDD

Pulse Width of Spikes That Must Be

Suppressed by the Input Filter, tSPIKE

SDA (WHEN OUTPUTTING DATA)

Output Logic 0 Voltage at 3 mA Sink Current

0.4

Output Fall Time from VIHMIN to VILMAX with

a Bus Capacitance from 10 pF to 400 pF

20 + 0.1 CB1

250

TIMING

Note that all I2C timing values are referred to

VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD)

Clock Rate (SCL, fI2C)

400

kHz

Bus Free Time Between a Stop and Start

Condition, tIDLE

1.3

µs

Setup Time for a Repeated Start Condition,

tSET; STR

0.6

µs

Hold Time (Repeated) Start Condition, tHLD;STR

0.6

µs

After this period, the first clock pulse is

generated

Setup Time for Stop Condition, tSET; STP

0.6

µs

Low Period of the SCL Clock, tLOW

1.3

µs

High Period of the SCL Clock, tHIGH

0.6

µs

SCL, SDA Rise Time, tRISE

20 + 0.1 CB1

300

SCL, SDA Fall Time, tFALL

20 + 0.1 CB1

300

Data Setup Time, tSET; DAT

100

Data Hold Time, tHLD; DAT

100

880

This is a minor deviation from the original I²C

specification of 0 ns minimum2

Capacitive Load for Each Bus Line, CB1

400

CB is the capacitance of one bus line in picofarads (pF).

According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL

falling edge.

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AD9524/PCBZ 数据表(PDF) 11 Page - Analog Devices

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