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AD9524/PCBZ 数据表(PDF) 46 Page - Analog Devices

部件名 AD9524/PCBZ
功能描述  Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs
PDF  56 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9524/PCBZ 数据表(HTML) 46 Page - Analog Devices

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AD9524
Data Sheet
Rev. E | Page 46 of 56
Table 43. PLL1 Miscellaneous Control
Address
Bits
Bit Name
Description
0x01C
7
Enable REFB R divider
independent division control
1: REFB R divider is controlled by Register 0x012 and Register 0x013.
0: REFB R divider is set to the same setting as the REFA R divider (Register 0x010
and Register 0x011). This requires that, for the loop to stay locked, the REFA and
REFB input frequencies must be the same.
6
OSC_CTRL control voltage to
VCC/2 when reference clock fails
High permits the OSC_CTRL control voltage to be forced to midsupply when the
feedback or input clocks fail. Low tristates the charge pump output.
1: OSC_CTRL control voltage goes to VCC/2.
0: OSC_CTRL control voltage tracks the tristated (high impedance) charge pump
(through the buffer).
5
Reserved
Reserved.
[4:2]
Reference selection mode
Programs the REFA, REFB mode selection (default = 000).
REF_SEL
Pin
Bit 4
Bit 3
Bit 2
Description
X1
0
0
0
Nonrevertive: stay on REFB.
X1
0
0
1
Revert to REFA.
X1
0
1
0
Select REFA.
X1
0
1
1
Select REFB.
0
1
X1
X1
REF_SEL pin = 0 (low): REFA.
1
1
X1
X1
REF_SEL pin = 1 (high): REFB.
[1:0]
Reserved
0: reserved (default).
1
X = don’t care.
Table 44. PLL1 Loop Filter Zero Resistor Control
Address
Bits
Bit Name
Description
0x01D
[7:4]
Reserved
Reserved.
[3:0]
PLL1 loop filter, RZERO
Programs the value of the zero resistor, RZERO.
Bit 3
Bit 2
Bit 1
Bit 0
RZERO Value (kΩ)
0
0
0
0
883
0
0
0
1
677
0
0
1
0
341
0
0
1
1
135
0
1
0
0
10
0
1
0
1
10
0
1
1
0
10
0
1
1
1
10
1
0
0
0
Use external resistor



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