AD9524SLASHPCBZ datasheet(9/56 Pages) AD

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Data Sheet

AD9524

Rev. E | Page 9 of 56

TIMING ALIGNMENT CHARACTERISTICS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT TIMING SKEW

Delay off on all outputs; maximum deviation

between rising edges of outputs; all outputs are on,

unless otherwise noted.

Between LVPECL, HSTL, and LVDS Outputs

234

Between CMOS Outputs

100

300

Single-ended true phase high-Z mode

Adjustable Delay

Steps

Resolution step; for example, 8 × 0.5/1 GHz

Resolution Step

500

½ period of 1 GHz

Zero Delay

Between Input Clock Edge on REFA or

REFB to ZD_IN Input Clock Edge,

External Zero Delay Mode

150

500

PLL1 settings: PFD = 7.68 MHz, ICP = 63.5 µA, RZERO = 10 kΩ,

antibacklash pulse width is at maximum, BW = 40 Hz,

REFA and ZD_IN are set to differential mode

JITTER AND NOISE CHARACTERISTICS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT ABSOLUTE RMS TIME JITTER

Application example based on a typical setup

(see Table 3); f = 122.88 MHz

LVPECL Mode, HSTL Mode, LVDS Mode

125

Integrated BW = 200 kHz to 5 MHz

136

Integrated BW = 200 kHz to 10 MHz

169

Integrated BW = 12 kHz to 20 MHz

212

Integrated BW = 10 kHz to 61 MHz

223

Integrated BW = 1 kHz to 61 MHz

PLL2 CHARACTERISTICS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO (ON CHIP)

Frequency Range

3600

4000

MHz

Gain

MHz/V

PLL2 FIGURE OF MERIT (FOM)

−226

dBc/Hz

MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

Minimum and Low

250

MHz

Maximum and High

125

MHz

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