AD9524SLASHPCBZ datasheet(50/56 Pages) AD

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AD9524

Data Sheet

Rev. E | Page 50 of 56

Reserved (Address 0x190)

Table 51. Reserved Register

Address

Bits

Bit Name

Description

0x190

[7:5]

Reserved

Reserved. The default value for this register is 0x00. It is recommended to write a value

of 0x20 to this register.

Clock Distribution (Address 0x196 to Address 0x1A1, Address 0x1AE to Address 0x1B3, Address 0x1BA, and Address

0x1BB)

Table 52. Channel 0 to Channel 5 Control (This same map applies to all six channels.)

Address

Bits

Bit Name

Description

0x196

Invert divider output

Inverts the polarity of the divider’s output clock.

Ignore sync

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Power-down channel

1: powers down the entire channel.

0: normal operation.

Lower power mode

(differential modes only)

Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This

reduction may result in power savings, but at the expense of performance. Note that

this bit does not affect output swing and current, just the internal driver power.

1: low strength/lower power.

0: normal operation.

[3:0]

Driver mode

Driver mode.

Bit 3

Bit 2

Bit 1

Bit 0

Driver Mode

Tristate output

LVPECL (8 mA)

LVDS (3.5 mA)

LVDS (7 mA)

HSTL-0 (16 mA)

HSTL-1 (8 mA)

CMOS (both outputs in phase)

+ Pin: true phase relative to divider output

− Pin: true phase relative to divider output

CMOS (opposite phases on outputs)

+ Pin: true phase relative to divider output

− Pin: complement phase relative to divider output

CMOS

+ Pin: true phase relative to divider output

− Pin: high-Z

CMOS

+ Pin: high-Z

− Pin: true phase relative to divider output

CMOS

+ Pin: high-Z

− Pin: high-Z

CMOS (both outputs in phase)

+ Pin: complement phase relative to divider output

− Pin: complement phase relative to divider output

CMOS (both outputs out of phase)

+ Pin: complement phase relative to divider output

− Pin: true phase relative to divider output

CMOS

+ Pin: complement phase relative to divider output

− Pin: high-Z

CMOS

+ Pin: high-Z

− Pin: complement phase relative to divider output

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AD9524/PCBZ 数据表(PDF) 50 Page - Analog Devices

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