AD9524SLASHPCBZ datasheet(51/56 Pages) AD

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Data Sheet

AD9524

Rev. E | Page 51 of 56

Address

Bits

Bit Name

Description

Tristate output

0x197

[7:0]

Channel divider, Bits[7:0] (LSB)

Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1

is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).

0x198

[7:2]

Divider phase

Divider initial phase after a sync is asserted relative to the divider input clock (from the

VCO divider output). LSB = ½ of a period of the divider input clock.

Phase = 0: no phase offset.

Phase = 1: ½ period offset, …

Phase = 63: 31 period offset.

[1:0]

Channel divider, Bits[9:8] (MSB)

10-bit channel divider, Bits[9:8] (MSB).

Table 53. PLL1 Output Control (PLL1_OUT, Pin 46)

Address

Bits

Bit Name

Description

0x1BA

[7:5]

Reserved

PLL1 output CMOS driver

strength

CMOS driver strength

1: weak

0: strong

[3:0]

PLL1 output divider

0000: divide-by-1

0001: divide-by-2 (default)

0010: divide-by-4

0100: divide-by-8

1000: divide-by-16

No other inputs permitted

Table 54. PLL1 Output Channel Control

Address

Bits

Bit Name

Description

0x1BB

PLL1 output driver power-down

[6:2]

Reserved

Route VCXO clock to

Channel 1 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input

0: channel uses VCO divider output clock

Route VCXO clock to

Channel 0 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input

0: channel uses VCO divider output clock

Readback (Address 0x22C to Address 0x22D)

Table 55. Readback Registers (Readback 0 and Readback 1)

Address

Bits

Bit Name

Description

0x22C

Status PLL2 reference clock

1: OK

0: off/clocks are missing

Status PLL1 feedback clock

1: OK

0: off/clocks are missing

Status VCXO

1: OK

0: off/clocks are missing

Status REF_TEST

1: OK

0: off/clocks are missing

Status REFB

1: OK

0: off/clocks are missing

Status REFA

1: OK

0: off/clocks are missing

Lock detect PLL2

1: locked

0: unlocked

Lock detect PLL1

1: locked

0: unlocked

AD9524/PCBZ 数据表(PDF) 51 Page - Analog Devices

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AD9524/PCBZ 数据表(PDF) 51 Page - Analog Devices

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