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ADMCF341 数据表(PDF) 33 Page - Analog Devices

部件名 ADMCF341
功能描述  28-Lead Flash and ROM Memory, Mixed-Signal DSPs with Enhanced Analog Front End
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADMCF341 数据表(HTML) 33 Page - Analog Devices

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REV. A
ADMC(F)341
–33–
ADC MUX
CONTROL
0 = BOOT MODE
1 = UART MODE
SPORT1 MODE
SELECT
0 = DISABLE
1 = ENABLE
PWMSYNC
INTERRUPT
0 = DISABLE
1 = ENABLE
PWMTRIP
INTERRUPT
0
0
0
0
0
0
00
0
0
0
SYSSTAT (R)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0 = LOW
1 = HIGH
DM (0x2016)
0 = NORMAL
1 = WATCHDOG RESET
OCCURRED
PWMTRIP
PIN STATUS
WATCHDOG
STATUS
PWM TIMER
STATUS
0 = 1ST HALF OF PWM
CYCLE
1 = 2ND HALF OF PWM
CYCLE
0
0
00
0
0
0
00
0
0
00
0
0
0
MODECTRL (R/W)
DM (0x2015)
0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC MUX CONTROL
00 VAUX0
01 VAUX1
10 VAUX2
11 VREF
0
0
00
0
0
0
00
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
00
IRQFLAG (R)
PWMTRIP INTERRUPT
PWMSYNC INTERRUPT
DM (0x2017)
0
0
0
0
0
0
00
0
0
00
0
0
00
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WDTIMER (W)
DM (0x2018)
01
0 = NO INTERRUPT
1 = INTERRUPT
OCCURRED
PWM UPDATE
MODE SELECT
ADC
COUNTER
0 = CLKIN RATE
1 = CLKOUT RATE
AUX PWM
MODE SELECT
CHANNEL 1
SELECTION
0 = OFFSET MODE
1 = INDEPENDENT MODE
0 = ISENSE
1 = VOLTAGE
CHANNEL 2
SELECTION
0 = ISENSE
1 = VOLTAGE
CHANNEL 3
SELECTION
0 = ISENSE
1 = VOLTAGE
SPORT 0
MODE SELECT
0 = SPORT MODE
1 = UART MODE
SPORT 0
SPI MODE
0 = SPORT
1 = SPI MODE
SPI CLOCK
POLARITY
0 = STANDARD
1 = REVERSE
SPI CLOCK
PHASE
0 = PHA0
1 = PHA1
NOT USED IN ADMCF341
SET BIT TO ZERO
Figure 29. Configuration of Status/Control Registers
Default bit values are shown; if no value is shown, the bit field is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written as shown.



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