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ADMCF341 数据表(PDF) 14 Page - Analog Devices |
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ADMCF341 数据表(HTML) 14 Page - Analog Devices |
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14 / 36 page  REV. A –14– ADMC(F)341 PWMSYNC AH AL PWMCHA PWMCHA 2 PWMDT PWMSYNCWT + 1 2 PWMDT SYSSTAT (3) PWMTM PWMTM Figure 7. Typical PWM Outputs of Three-Phase Timing Unit in Single Update Mode Each switching edge is moved by an equal amount (PWMDT tCK) to preserve the symmetrical output patterns. The PWMSYNC pulse, whose width is set by the PWMSYNCWT register, is also shown. Bit 3 of the SYSSTAT register indicates which half cycle is active. This can be useful in double update mode, as will be discussed later. The resultant on-times of the PWM signals shown in Figure 7 may be written as: T PWMCHA PWMDT t AH CK =× − × 2( ) T PWMTM PWMCHA PWMDT t AL CK =× − − × 2( ) The corresponding duty cycles are: d T T PWMCHA PWMDT PWMTM AH AH S == − d T T PWMTM PWMCHA PWMDT PWMTM AL AL S == −− Obviously, negative values of TAH and TAL are not permitted because the minimum permissible value is zero, corresponding to a 0% duty cycle. In a similar fashion, the maximum value is TS, corresponding to a 100% duty cycle. The output signals from the timing unit for operation in double update mode are shown in Figure 8. This illustrates a completely general case where the switching frequency, dead time, and duty cycle are all changed in the second half of the PWM period. Of course, the same value for any or all of these quantities could be used in both halves of the PWM cycle. However, it can be seen that there is no guarantee that symmetrical PWM signals will be produced by the timing unit in this double update mode. Additionally, it is seen that the dead time is inserted into the PWM signals in the same way as in single update mode. PWMCHA2 2 PWMDT1 2 PWMDT2 PWMSYNCWT2 + 1 PWMCHA1 PWMTM1 PWMTM2 PWMSYNCWT1 + 1 AH AL PWMSYNC SYSSTAT (3) Figure 8. Typical PWM Outputs of Three-Phase Timing Unit in Double Update Mode In general, the on-times of the PWM signals in double update mode are defined by: T PWMCHA PWMCHA PWMDT PWMDT T AH CK = +− −× ( ) 12 12 T PWMTM PWMTM PWMCHA PWMCHA PWMDT PWMDT t AL CK = +− − −− × ( ) 12 1 212 d T T PWMCHA PWMCHA PWMTM PWMTM PWMDT PWMDT PWMTM PWMTM AH AH S == + + − + + 12 12 12 12 d T T PWMTM PWMTM PWMCHA PWMTM PWMTM PWMCHA PWMDT PWMCHA PWMTM PWMTM AL AL S == ++ + − ++ + 12 1 12 21 1 12 because for the completely general case in double update mode, the switching period is given by: TPWMTM PWMTM t SCK =+ × () 12 Again, the values of TAH and TAL are constrained to lie between zero and TS. PWM signals similar to those illustrated in Figure 7 and Figure 8 can be produced on the BH, BL, CH, and CL outputs by programming the PWMCHB and PWMCHC registers in a manner identical to that described for PWMCHA. The PWM controller does not produce any PWM outputs until all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC registers have been written to at least once. After these registers have been written, the counters in the three-phase timing unit are enabled. Writing to these registers also starts the main PWM timer. If, during initialization, the PWMTM register is written before the PWMCHA, PWMCHB, and PWMCHC registers, the first PWMSYNC pulse (and interrupt if enabled) will be generated (1.5 × tCK × PWMTM) seconds after the initial write to the PWMTM register in single update mode. In double update mode, the first PWMSYNC pulse will be generated (tCK × PWMTM) seconds after the initial write to the PWMTM register in single update mode. |
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