ADMCF341_15 datasheet(16/36 Pages) AD

16 / 36 page

REV. A

–16–

ADMC(F)341

PWMCHA = PWMCHB

PWMTM

PWMDT

Figure 9. An Example of PWM Signals Suitable for

ECM Control. PWMCHA = PWMCHB, BH/BL are a

Crossover Pair. AL, BH, CH, and CL Outputs are

Disabled. Operation is in Single Update Mode.

Gate Drive Unit: PWMGATE Register

The gate drive unit of the PWM controller adds features that

simplify the design of isolated gate drive circuits for PWM

inverters. If a transformer-coupled power device gate drive

amplifier is used, the active PWM signal must be chopped at a

high frequency. The PWMGATE register allows the programming

of this high frequency chopping mode. The chopped active

PWM signals may be required for the high side drivers only, for

the low side drivers only, or for both the high side and low side

switches. Therefore, independent control of this mode for both

high side and low side switches is included with two separate

control bits in the PWMGATE register.

Typical PWM output signals with high frequency chopping

enabled on both high side and low side signals are shown in

Figure 10. Chopping of the high side PWM outputs (AH, BH

and CH) is enabled by setting Bit 8 of the PWMGATE register.

Chopping of the low side PWM outputs (AL, BL, and CL) is

enabled by setting Bit 9 of the PWMGATE register. The high

chopping frequency is controlled by the 8-bit word (GDCLK)

written to Bits 0 to 7 of the PWMGATE register. The period

and the frequency of this high frequency carrier are:

GDCLK

CHOP

=×

()+

[]×

GDCLK

CHOP

CLKOUT

×+

()

[]

The GDCLK value may range from 0 to 255, corresponding to

a programmable chopping frequency rate from 19.5 kHz to 5 MHz

for a 20 MHz CLKOUT rate. The gate drive features must be

programmed before operation of the PWM controller and typically

are not changed during normal operation of the PWM control-

ler. Following a reset, by default, all bits of the PWMGATE

PWMTM

(GDCLK+1)]

PWMDT

PWMCHA

Figure 10. Typical PWM Signals With High

Frequency Gate Chopping Enabled on Both

High Side and Low Side Switches. (GDCLK is

the Integer Equivalent of the Value in Bits 0

to 7 of the PWMGATE Register.)

PWM Shutdown

In the event of external fault conditions, it is essential that the

PWM system be instantaneously shut down. Two methods of

sensing a fault condition are provided by the ADMC(F)341.

For the ﬁrst method, a low level on the

PWMTRIP pin initiates

an instantaneous, asynchronous (independent of DSP clock)

shutdown of the PWM controller. This places all six PWM

outputs in the OFF state, disables the PWMSYNC pulse and

associated interrupt signal, and generates a

PWMTRIP inter-

rupt signal. The

PWMTRIP pin has an internal pull-down

resistor so that even if the pin becomes disconnected, the PWM

outputs will be disabled. The state of the

PWMTRIP pin can be

read from Bit 0 of the SYSSTAT register.

The second method for detecting a fault condition is through

the ISENSE pins of the analog block of the ADMC(F)341. When

the voltage at any of the ISENSE pins exceeds the trip threshold

(high or low), or the ISENSE pin is in high impedance (floating),

PWMTRIP will be internally pulled low. The negative edge of

the internal

PWMTRIP will generate a shutdown in the same

manner as a negative edge on pin

PWMTRIP.

It is possible through software to initiate a PWM shutdown by

writing to the 1-bit read/write PWMSWT register (0x2061).

Writing to this bit generates a PWM shutdown in a manner

identical to the

PWMTRIP or I

SENSE pins. Following a PWM

shutdown, it is possible to determine if the shutdown was gener-

ated from hardware or software by reading the same PWMSWT

Restarting the PWM after a fault condition is detected requires

clearing the fault and reinitializing the PWM. Clearing the fault

requires

PWMTRIP to return to a high state and I

SENSE to re-

turn to a voltage in the ISENSE trip level range. After the fault has

been cleared, the PWM can be restarted by writing to registers

PWMTM, PWMCHA, PWMCHB, and PWMCHC. After the

fault is cleared and the PWM registers are initialized, internal

timing of the three-phase timing unit will resume, and the new

duty cycle values will be latched on the next rising edge of

PWMSYNC.

PWM Registers

The conﬁguration of the PWM registers is described in Figures

23, 24, and 27. The parameters of the PWM block are tabu-

lated in Table V.

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