ADMCF341_15 datasheet(7/36 Pages) AD

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REV. A

ADMC(F)341

–7–

GENERAL DESCRIPTION

The ADMC(F)341 is a low cost, single-chip, DSP-based

controller suitable for permanent magnet synchronous motors,

ac induction motors, and brushless dc motors. The ADMC(F)341

integrates a 20 MHz, fixed-point DSP core with a complete set

of motor control and system peripherals that permits fast,

efficient development of motor controllers.

The DSP core of the ADMC(F)341 is completely code compat-

ible with the ADSP-21xx DSP family and combines three

computational units, data address generators, and a program

sequencer. The computational units are an ALU, a multiplier/

accumulator (MAC), and a barrel shifter. There are special

instructions for bit manipulation, multiplication (x squared),

biased rounding, and global interrupt masking. The system

peripherals are the power-on reset circuit (POR), the watchdog

timer, and two synchronous serial ports. The serial ports are

configurable and double buffered, with hardware support for

UART, SCI, and SPI port emulation. The ADMC(F)341 pro-

vides 512

24-bit program memory RAM, 4K

24-bit

program memory ROM, 4K

24-bit program FLASH memory,

and 512

16-bit data memory RAM. The user code can be

stored and executed from the flash memory. The program and

data memory RAM can be used for dynamic data storage or

can be loaded through the serial port from an external device

as in other ADMCxxx family parts. The program memory

ROM contains a monitor function as well as useful routines for

erasing, programming, and verifying the flash memory.

The motor control peripherals of the ADMC(F)341 provide a

12-bit analog data acquisition system with six analog input

channels with three dedicated ISENSE inputs (combining internal

amplification, sampling, and overcurrent PWM shutdown

features) and an internal voltage reference. In addition, a three-

phase, 16-bit, center-based PWM generation unit can be used

to produce high accuracy PWM signals with minimal processor

overhead. The ADMC(F)341 also contains two 16-bit auxiliary

PWM timer outputs and nine lines of digital I/O.

Because the ADMC(F)341 has a limited number of pins, func-

tions such as the auxiliary PWM timers and the serial

communication ports are multiplexed with the nine program-

mable digital input/output (PIO) pins. The pin functions can be

independently selected to allow maximum flexibility for differ-

ent applications.

DSP CORE ARCHITECTURE OVERVIEW

Figure 3 is an overall block diagram of the DSP core of the

ADMC(F)341. The flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle (50 ns with a 10 MHz

CLKIN) the DSP core can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This all takes place while the processor continues to:

• Receive and transmit through the serial ports

• Decrement the interval timer

• Generate three-phase PWM waveforms for a power inverter

• Generate two signals using the 16-bit auxiliary PWM timers

• Acquire four analog signals

• Decrement the watchdog timer

PM ROM

PM RAM

512

BUS

EXCHANGE

COMPANDING

CIRCUITRY

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

DM RAM

512

R BUS

DMA BUS

PMA BUS

DMD BUS

PMD BUS

INSTRUCTION

INPUT REGS

OUTPUT REGS

SHIFTER

CONTROL

LOGIC

SERIAL

PORT

RECEIVE REG

TRANSMIT REG

TIMER

INPUT REGS

OUTPUT REGS

MAC

INPUT REGS

OUTPUT REGS

ALU

PROGRAM

SEQUENCER

FLASH

PROGRAM

MEMORY

Figure 3. DSP Core Block Diagram

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