ADMCF341_15 datasheet(27/36 Pages) AD

27 / 36 page

REV. A

ADMC(F)341

–27–

Table XIII. DSP Core Registers

Address (hex)

Name

Bits

Function

0x3FFF

SYSCNTL

[15 . . . 0]

System Control Register

0x3FFE

MEMWAIT

[15 . . . 0]

Memory Wait State Control Register

0x3FFD

TPERIOD

[15 . . . 0]

Interval Timer Period Register

0x3FFC

TCOUNT

[15 . . . 0]

Interval Timer Count Register

0x3FFB

TSCALE

[7 . . . 0]

Interval Timer Scale Register

0x3FFA

SPORT0_RX_WORDS1

[15 . . . 0]

SPORT0 Multichannel Word 1 Receive

0x3FF9

SPORT0_RX_WORDS0

[15 . . . 0]

SPORT0 Multichannel Word 0 Receive

0x3FF8

SPORT0_TX_WORDS1

[15 . . . 0]

SPORT0 Multichannel Word 1 Transmit

0x3FF7

SPORT0_TX_WORDS0

[15 . . . 0]

SPORT0 Multichannel Word 0 Transmit

0x3FF6

SPORT0_CTRL_REG

[15 . . . 0]

SPORT0 Control Register

0x3FF5

SPORT0_SCLKDIV

[15 . . . 0]

SPORT0 Clock Divide Register

0x3FF4

SPORT0_RFSDIV

[15 . . . 0]

SPORT0 Receive Frame Sync Divide

0x3FF3

SPORT0_AUTOBUF_CTRL

[15 . . . 0]

SPORT0 Autobuffer Control Register

0x3FF2

SPORT1_CTRL_REG

[15 . . . 0]

SPORT1 Control Register

0x3FF1

SPORT1_SCLKDIV

[15 . . . 0]

SPORT1 Clock Divide Register

0x3FF0

SPORT1_RFSDIV

[15 . . . 0]

SPORT1 Receive Frame Sync Divide

0x3FEF

SPORT1_AUTOBUF_CTRL

[15 ...0]

SPORT1 Autobuffer Control Register

FLASH MEMORY CONTROL REGISTER

0x2080

FLASH MEMORY ADDRESS REGISTER

0x2081

RESERVED

ALWAYS READ 0

ADDRESS 11

FLASH MEMORY DATA REGISTER LOW (FMDRL)

RESERVED

ALWAYS READ 0

0x2083

STATUS 5

DATA 7

FLASH MEMORY DATA REGISTER HIGH (FMDRH)

0x2082

DATA 23

MOST SIGNIFICANT BIT IS ON THE LEFT. FOR EXAMPLE, DATA23 IS BIT 15 OF FMDRH.

BOOT

MEMORY

FLASH

CODE

Figure 22. Conﬁguration of Flash Memory Registers

Default bit values are shown; if no value is shown, the bit ﬁeld is undeﬁned at reset.

Reserved bits are shown on a gray ﬁeld—these bits should always be written as shown.

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