ADMCF341_15 datasheet(18/36 Pages) AD

18 / 36 page

REV. A

–18–

ADMC(F)341

Following reset, VC = 0 at t = 0. This reset and the start of the

conversion process are initiated by the PWMSYNC pulse, as

shown in Figure 12. The width of the PWMSYNC pulse is

controlled by the PWMSYNCWT register and should be pro-

grammed according to Figure 13 to ensure complete resetting.

To compensate for IC process manufacturing tolerances (and to

adjust for capacitor tolerances), the current source of the

ADMC(F)341 is software-programmable. Using software to set

the magnitude of the ICONST current generator is accom-

plished by selecting one of eight steps over approximately 20%

current range.

PWMSYNC

COMPARATOR

OUTPUT

VCMAX

TVIL

TPWM – TCRST

TCRST

Figure 12. Analog Input Block Operation

The ADC system consists of four comparators and a single

timer that may be clocked at either the DSP rate or half the

DSP rate, depending on the setting of the ADCCNT bit (Bit 7)

of the MODECTRL register. When this bit is cleared, the timer

counts at a slower rate of CLKIN. When this bit is set, it counts

at CLKOUT or twice the rate of CLKIN. ADC1, ADC2, ADC3,

and ADCAUX are the registers that capture the conversion times,

which are the timer values when the associated comparator trips.

200

150

100

CHARGING CAPACITOR – nF

Figure 13. PWMSYNCWT Program Value

ADC Resolution

The ADC is intrinsically linked to the PWM block through the

PWMSYNC pulse’s control of the ADC conversion process.

Because of this link, the effective resolution of the ADC is a

function of both the PWM switching frequency and the rate at

which the ADC counter timer is clocked. For a CLKOUT

period of tCK and a PWM period of TPWM, the maximum count

of the ADC is given by:

Max Count

for MODECTRL Bit

Max Count

for MODECTRL Bit

PWM

CRST

PWM

CRST

=−

min

(, (

)

(, (

)

4095

where TPWM is equal to the PWM period if operating in single

update mode to half that period if operating in double update

mode. For an assumed CLKOUT frequency of 20 MHz and

PWMSYNC pulsewidth of 2.0

µs, the effective resolution of

the ADC block is tabulated for various PWM switching fre-

quencies in Table VII.

Table VII. ADC Resolution Examples

PWM

MODECTRL[7] = 0

MODECTRL[7] = 1

Frequency

Max

Effective

Max

Effective

(kHz)

Count

Resolution

Count

Resolution

2.4

4095

2480

>11

4095

1230

>10

2460

>11

535

1070

>10

380

760

Programmable Current Source

The ADMC(F)341 has an internal current source that is used

to charge an external capacitor, generating the voltage ramp

used for conversion. The magnitude of the output of the current

source circuit is subject to manufacturing variations and can

vary from one device to the next. Therefore, the ADMC(F)341

includes a programmable current source whose output can

always be tuned to within 5% of the target 100

µA. A 3-bit

ment. The output current is proportional to the value written to

the register: 0x0 produces the minimum output and 0x7 produces

the maximum output. The default value of ICONST_TRIM after

reset is 0x0.

Charging Capacitor Selection

The charging capacitor value is selected based on the sample

(PWM) frequency desired. A too-small capacitor value will reduce

the available resolution of the ADC by having the ramp voltage rise

rapidly and convert too quickly, not utilizing all possible counts

available in the PWM cycle. A too-large capacitor may not convert

in the available PWM cycle returning 0x000.

To select a charging capacitor use Figure 14. Select the sam-

pling frequency desired, determine if the current source is to be

tuned to a nominal 100

µA or left in the default (0x0 code) trim

state, then determine the proper charge capacitor off the appro-

priate curve.

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