ADMCF341_15 datasheet(9/36 Pages) AD

9 / 36 page

REV. A

ADMC(F)341

–9–

PIN FUNCTION DESCRIPTION

The ADMC(F)341 is available in a 28-lead SOIC package.

Table I describes the pins.

Table I. Pin List

Pin Group

No. of Input/

Name

Pins

Output Function

RESET

Processor Reset Input

SPORT1

I/O

Serial Port 1 Pins (DT1/FL1,

DR1, SCLK1/SCLK0

SPORT0

I/O

Serial Port 0 Pins (DT0, DR0

TFSO, SCLK1/SCLK0

CLKOUT

I/O

Processor Clock Output

CLKIN, XTAL

I, O

External Clock or Quartz

Crystal Connection Point

PORTA0–

I/O

Digital I/O Port Pins

PORTA8

AUX0–AUX1

Auxiliary PWM Outputs

AH–CL

PWM Outputs

PWMTRIP

PWM Trip Signal

ISENSE1–3

ISENSE Inputs

ISENSE3

VAUX0–VAUX2 3

Auxiliary Analog Inputs

ICONST

ADC Constant Current

Source

VDD

Power Supply

GND

Ground

NOTES

1Multiplexed pins, individually selectable through PORTA_SELECT

and PORTA_DATA registers.

2SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL

INTERRUPT OVERVIEW

The ADMC(F)341 can respond to 18 different interrupt sources

with minimal overhead, seven of which are internal DSP core

interrupts and 11 are from the motor control peripherals. The

seven DSP core interrupts are SPORT1 receive (or

IRQ0) and

transmit (or

IRQ1), SPORT0 receive and transmit, the internal

timer, and two software interrupts. The motor control peripheral

interrupts are the nine programmable I/Os and two from the

PWM (PWMSYNC pulse and

PWMTRIP). All motor control

interrupts are multiplexed into the DSP core through the

peripheral

IRQ2 interrupt. The interrupts are internally prioritized

and individually maskable. A detailed description of the entire

interrupt system of the ADMC(F)341 is presented later, following

a more detailed description of each peripheral block.

MEMORY MAP

The ADMC(F)341 has two distinct memory types: program

and data. In general, program memory contains user code and

coefficients, while the data memory is used to store variables

and data during program execution. Three kinds of program

memory are provided on the ADMC(F)341: RAM, ROM, and

FLASH. The motor control peripherals are memory mapped

into a region of the data memory space starting at 0x2000. The

complete program and data memory maps are given in Tables II

and III, respectively.

Table II. Program Memory Map

Memory

Address Range

Type

Function

0x0000–0x002F

RAM

Internal Vector Table

0x0030–0x01FF

RAM

User Program Memory

0x0200–0x07FF

Reserved

0x0800–0x17FF

ROM

Reserved Program Memory

0x1800–0x1FFF

Reserved

0x2000–0x20FF

FLASH

User Program Memory

Sector 0

0x2100–0x21FF

FLASH

User Program Memory

Sector 1

0x2200–0x2FFF

FLASH

User Program Memory

Sector 2

0x3000–0x3FFF

Reserved

Table III. Data Memory Map

Memory

Address Range

Type

Function

0x0000–0x1FFF

Reserved

0x2000–0x20FF

Memory Mapped Registers

0x2100–0x37FF

Reserved

0x3800–0x39FF

RAM

User Data Memory

0x3A00–0x3BFF

RAM

Reserved

0x3C00–0x3FFF

Memory Mapped Registers

FLASH MEMORY SUBSYSTEM

The ADMC(F)341 has 4K

24-bits of user-programmable,

nonvolatile flash memory. A flash programming utility is provided

with the development tools, which perform the basic device

programming operations: erase, program, and verify.

The flash memory array is portioned into three asymmetrically

sized sectors of 256 words, 256 words, and 3584 words, labeled

sector 0, sector 1, and sector 2, respectively. These sectors are

mapped into external program memory address space.

Four flash memory interface registers are connected to the DSP.

These 16-bit registers are mapped into the register area of data

memory space. They are named flash memory control register

(FMCR), flash memory address register (FMAR), flash memory

data register low (FMDRL), and flash memory data register

high (FMDRH). These registers are diagrammed in Figure 22.

They are used by the flash memory programming utility. The

user program may read these registers, but should not modify

them directly. The flash programming utility provides a complete

interface to the flash memory.

It should be noted that the core accesses flash memory through

an external memory interface that multiplexes the program

memory and data memory buses into a single external bus.

Therefore, if more than one external transfer must be made in the

same instruction, there will be at least one overhead cycle required.

ADMCF341 数据表(PDF) 9 Page - Analog Devices

ADMCF341 数据表(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载

链接网址

ADMCF341 数据表(PDF) 9 Page - Analog Devices

ADMCF341 数据表(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表 下载

链接网址

数据表下载