ADMCF341_15 datasheet(22/36 Pages) AD

22 / 36 page

REV. A

–22–

ADMC(F)341

alternate function of PORTA7 is selected by Bit 14 of the

PORTA_SELECT register. The second alternate function of

PORTA8 is selected by Bit 15 of the PORTA_SELECT register.

The second alternate function of the PORTA4 and PORTA5

pins is selected by Bit 4 of MODECTRL Register (SPORT1

mode: boot mode/UART mode).

Once PIO functionality has been selected for any or all of these nine

pins, the direction may be set by the 9-bit PORTA_DIR register.

Clearing any bit configures the corresponding PIO line as an input,

while setting the bit configures it as an output. By default, following

a reset, all bits of PORTA_DIR are cleared, configuring the PIO

lines as inputs. The data of the PORTA0 to PORTA8 lines is con-

trolled by the PORTA_DATA register. These registers can be used

to read data from those PIO lines configured as inputs and write data

to those configured as outputs. Any of the nine pins that have been

configured for PIO functionality can be made to act as an interrupt

source by setting the appropriate bit of the PORTA_INTEN register.

To act as an interrupt source, the pin must also be configured as an

input. An interrupt is generated upon a change of state (low-to-high

transition or high-to-low transition) on any input that has been

configured as an interrupt source. Following a change of state event

on any such input, the corresponding bit is set in the

PORTA_FLAG, register and a common PIO interrupt is generated.

Reading the PORTA_FLAG register permits determining

the interrupt source. Reading the PORTA_FLAG register

automatically clears all bits of the registers. Following power-

on or reset, all bits of PORTA_INTEN are cleared so that no

interrupts are enabled.

Each PIO line has an internal pull-down resistor so that following

power-on or reset, all nine lines are configured as input PIOs

and will be read as logic lows if left unconnected.

PIO Registers

The configuration of all registers of the PIO system is shown in

Figure 25.

INTERRUPT CONTROL

The ADMC(F)341 can respond to 18 different interrupt sources

with minimal overhead. Seven of these interrupts are internal

DSP core interrupts and 11 are from the on-chip peripherals.

The seven DSP core interrupts are SPORT0 receive and

transmit, SPORT1 receive (or IRQ0) and transmit (or IRQ1),

the internal timer, and two software interrupts. The motor

control interrupts are the nine PORTA PIOs and two from the

PWM block (PWMSYNC pulse and

PWMTRIP). All the on-chip

peripheral interrupts are multiplexed into the DSP core via the

peripheral

IRQ2 interrupt. They are also internally prioritized

and individually maskable. The start address in the interrupt

vector table for the ADMC(F)341 interrupt sources is shown in

Table X. The interrupts are listed from highest to lowest prior-

ity. The PWMSYNC interrupt is triggered by a low-to-high

transition on the PWMSYNC pulse. The

PWMTRIP interrupt

is triggered on a high-to-low transition on the

PWMTRIP pin.

A PIO interrupt is detected on any change of state (high-to-low

or low-to-high) on the PIO lines.

The entire interrupt control system of the ADMC(F)341 is

configured and controlled by the IFC, IMASK, and ICNTL

registers of the DSP core, the IRQFLAG register for the

PWMSYNC and

PWMTRIP interrupts, and PORTA_FLAG

Table X. Interrupt Vector Addresses

Interrupt Source

Interrupt Vector Address

PWMTRIP

0x002C (Highest Priority)

Peripheral Interrupt (

IRQ2)

0x0004

PWMSYNC

0x000C

PIO

0x0008

Software Interrupt 1

0x0018

Software Interrupt 0

0x001C

SPORT0 Transmit Interrupt

0x0010

SPORT0 Receive Interrupt

0x0014

SPORT1 Transmit Interrupt (or

IRQ1) 0x0020

SPORT1 Receive Interrupt (or

IRQ0)

0x0024

Timer

0x0028 (Lowest Priority)

Interrupt Masking

Interrupt masking (or disabling) is controlled by the IMASK

that must be set to enable the various interrupt sources. If any

peripheral interrupt is to be enabled, the

IRQ2 interrupt enable

bit (Bit 9) of the IMASK register must be set. The configuration

of the IMASK register of the ADMC(F)341 is shown in Figure 30.

Table IX. Port A Multiplexing

PORTA Pin

First Alternate Function (Peripheral)

Second Alternate Function (Peripheral)

PORTA8

AUX0 (Auxiliary PWM Output)

CLKOUT (System CLOCK)

PORTA7

AUX1 (Auxiliary PWM Output)

PWMSYNC (PWM)

PORTA6

DR1 (Data Receive SPORT1)

None

PORTA5

FL1 (Flag Out SPORT1)

DT1 (Data Transmit SPORT1)

PORTA4

SCLK1 (Serial Clock SPORT1)

SCLK0 (Serial Clock SPORT0)

PORTA3

TFS0 (Transmit Frame Sync SPORT0)

None

PORTA2

RFS0 (Receive Frame Sync SPORT0)

None

PORTA1

DT0 (Data Transmit SPORT0)

None

PORTA0

DR0 (Data Receive SPORT0)

None

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