GH2

SH2

GL2

SP

SN

GL1

AVDD

DVDD

nFAULT

SNSOUT

SO

IDRIVE

24

23

22

21

20

19

7

8

9

10

11

12

0.01 µF

1 µF

0.1 µF

R1

R2

68 k

Ÿ

10 k

Ÿ

10 k

Ÿ

1 µF

1 µF

50 m

Ÿ

VBAT

VBAT

BDC

Boost

0.1 µF

10 µF

+

AVDD

C1

+

GND

(PPAD)

DRV8701

www.ti.com

SLVSCX5B – MARCH 2015 – REVISED JULY 2015

8.2.2 Alternate Application

In this example, the DRV8701 is powered from a supply that is boosted above VBAT. This allows the system to

work at lower VBAT voltages, but requires the user to disable OCP monitoring.

Figure 40. DRV8701 on Boosted Supply

8.2.2.1 Design Requirements

Table 11 gives design input parameters for system design.

Table 11. Design Parameters

Design Parameter

Reference

Example Value

12 V nominal

Battery voltage

VBAT

Minimum operation: 4.0 V

VM = 7 V when VBAT < 7 V

DRV8701 supply voltage

VM

VM = VBAT when VBAT

≥ 7 V

FET total gate charge

42 nC

FET gate-to-drain charge

11 nC

Motor current chopping level

3 A

8.2.3 Detailed Design Procedure

8.2.3.1 IDRIVE Configuration

Because the VM supply to the DRV8701 is different from the external H-bridge supply VBAT, the designer must

disable the overcurrent monitor to prevent false overcurrent detection. The designer must place a 68-k

Ω resistor

between the IDRIVE pin and AVDD.

IDRIVE is fixed at 25-mA source and 50-mA sink in this mode.

So, the rise time is 11 nC / 25 mA = 440 ns.

Copyright © 2015, Texas Instruments Incorporated

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