GH2

GL2

SH2

Gate

Drive

BDC

SP

Logic

PH/IN1

EN/IN2

nSLEEP

SNSOUT

+

-

SO

VREF

SN

VM

Control

Inputs

nFAULT

Outputs

GH1

GL1

SH1

Gate

Drive

330

DRV8701

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SLVSCX5B – MARCH 2015 – REVISED JULY 2015

7.3.2 Half-Bridge Operation

The DRV8701 can be used to drive only a single half-bridge instead of a full H-bridge. To operate in this mode,

leave GH1 and GL1 disconnected. Also, connect a 1/10 W, 330-

Ω 5% resistor from SH1 to GND.

Figure 20. Half-H Bridge Operation Mode

For the DRV8701E, this mode is controlled by tying the PH pin low. Table 3 gives the control scheme. EN = 1

enables the high-side FET, and EN = 0 enables the low-side FET. EN = 1 and PH = 1 is an invalid state.

Table 3. DRV8701E (PH/EN) Control Interface for Half-H Bridge Mode

nSLEEP

EN

PH

SH2

AVDD/DVDD

Description

0

X

X

High-Z

Disabled

Sleep mode; disabled High-Z

1

0

X

L

Enabled

Brake, low-side slow decay

1

1

0

H

Enabled

Drive (Current SH2

→ GND)

1

1

1

Invalid state

For the DRV8701P, Table 4 gives the control scheme. IN1 = 1 and IN2 = 0 is an invalid state.

Table 4. DRV8701P (PWM) Control Interface for Half-H Bridge Mode

nSLEEP

IN1

IN2

SH2

AVDD/DVDD

Description

0

X

X

High-Z

Disabled

Sleep mode; disabled High-Z

1

0

0

High-Z

Enabled

Coast; disabled High-Z

1

0

1

H

Enabled

Drive (current SH2

→ GND)

1

1

0

Invalid state

1

1

1

L

Enabled

Brake; low-side slow decay

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