GH1

GL1

SH1

VGHS

VGLS

Pre-Drive

GH2

GL2

SH2

VGHS

VGLS

VM

BDC

Logic

PH or IN1

EN or IN2

SP

SN

nSLEEP

VM

Pre-Drive

DRV8701

SLVSCX5B – MARCH 2015 – REVISED JULY 2015

www.ti.com

7.3.5 PWM Motor Gate Drivers

The DRV8701 contains gate drivers for a single H-bridge with external NMOS FETs. Figure 24 shows a block

diagram of the gate driver circuitry.

Figure 24. PWM Motor Gate Drivers

Gate drivers inside the DRV8701 directly drive N-channel MOSFETs, which drive the motor current. The high-

side gate drive is supplied by the charge pump, while the low-side gate drive voltage is generated by an internal

regulator.

The peak drive current of the gate drivers is adjustable through the IDRIVE pin. Peak source currents may be set

to 6, 12.5, 25, 100, or 150 mA. The peak sink current is approximately 2× the peak source current. Adjusting the

peak current changes the output slew rate, which also depends on the FET input capacitance and gate charge.

voltage onto the IDRIVE pin (see Table 6 for details).

Fast switching times can cause extra voltage noise on VM and GND. This can be especially due to a relatively

slow reverse-recovery time of the low-side body diode, where it conducts reverse-bias momentarily, being similar

to shoot-through. Slow switching times can cause excessive power dissipation since the external FETs take a

longer time to turn on and turn off.

18

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