1 µF

0.1 µF

24

23

22

21

20

7

8

9

10

11

12

AVDD

DVDD

nFAULT

SNSOUT

SO

IDRIVE

GL1

SN

SP

GL2

SH2

GH2

GND

(PPAD)

19

1 µF

1 µF

0.1 µF

D

D

D

D

G

S

S

S

S

D

D

D

D

G

S

S

S

S

S

G

D

D

D

D

S

S

S

G

D

D

D

D

10 µF

minimum

GND

GND

GND

+

DRV8701

www.ti.com

SLVSCX5B – MARCH 2015 – REVISED JULY 2015

10 Layout

10.1 Layout Guidelines

Bypass the VM pin to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF

rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane

connection to the device GND pin.

Bypass the VM pin to ground using a bulk capacitor rated for VM. This component may be an electrolytic. This

capacitance must be at least 10 µF. The bulk capacitor should be placed to minimize the distance of the high-

current path through the external FETs. The connecting metal trace widths should be as wide as possible, and

numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the

bulk capacitor to deliver high current.

Place a low-ESR ceramic capacitor in between the CPL and CPH pins. The value for this component is 0.1 µF

rated for VM. Place this component as close to the pins as possible.

Place a low-ESR ceramic capacitor in between the VM and VCP pins. The value for this component is 1 µF rated

for 16 V. Place this component as close to the pins as possible.

Bypass AVDD and DVDD to ground with ceramic capacitors rated at 6.3 V. Place these bypassing capacitors as

close to the pins as possible.

If desired, align the external NMOS FETs as shown in Figure 42 to facilitate layout. Route the SH2 and SH1 nets

to the motor.

10.2 Layout Example

Figure 42. Layout Recommendation

Copyright © 2015, Texas Instruments Incorporated

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