DRV8701PRGET datasheet(19/42 Pages) TI

19 / 42 page

QG gate charge (nC)

QGS

QGD

Remaining QG

VGHS

GHx

SHx

Pre-Drive

CGS

CGD

High-side

VGS

Low-side

VGS

High-side

gate drive

current

Low-side

gate drive

current

tDRIVE

IHOLD

DRV8701

www.ti.com

SLVSCX5B – MARCH 2015 – REVISED JULY 2015

When changing the state of the output, the peak current (IDRIVE) is applied for a short drive period (tDRIVE) to

charge the gate capacitance. After this time, a weaker current source (IHOLD) is used to keep the gate at the

desired state. When selecting the gate drive strength for a given external FET, the selected current must be high

enough to fully charge and discharge the gate during tDRIVE, or excessive power will be dissipated in the FET.

During high-side turn-on, the low-side gate is pulled low with a strong pull-down (ISTRONG). This prevents the low-

side FET QGS from charging and keeps the FET off, even when there is fast switching at the outputs.

The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and

low-side FETs from conducting at the same time. When switching FETs on, this handshaking prevents the high-

or low-side FET from turning on until the opposite FET has been turned off.

Figure 25. Gate Driver Output to Control External FETs

QGD Miller charge

When a FET gate is turned on, three different capacitances must be charged.

•

QGS – Gate-to-source charge

•

QGD – Gate-to-drain charge (miller charge)

•

Remaining QG

The FET output is slewing primarily during the QGD charge.

Figure 26. Example FET Gate Charging Profile

Submit Documentation Feedback

Product Folder Links: DRV8701

DRV8701PRGET 数据表(PDF) 19 Page - Texas Instruments

DRV8701PRGET 数据表(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载