IDRIVE

«««

IDRIVE

IDRIVE

«««

IDRIVE

AVDD

IDRIVE

AVDD

«««

IDRIVE

+

-

2.5V

+

-

1.3V

+

-

0.1V

+

-

3.7V

+

-

4.3V

AVDD

190k

Ÿ

310k

Ÿ

Digital

Core

DRV8701

SLVSCX5B – MARCH 2015 – REVISED JULY 2015

www.ti.com

7.3.6 IDRIVE Pin

The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or

forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is chosen.

The FET gate ramp directly affects the H-bridge output rise and fall time.

Tying IDRIVE to GND selects the lowest drive setting of 6-mA source and 12.5-mA sink. If this pin is left

unconnected, then the 100-mA source and 200-mA sink setting are selected.

If IDRIVE is shorted to AVDD, then the VDS OCP monitor on the high-side FETs is disabled. In this setting, the

gate driver is configured as 25-mA source and 50-mA sink.

Figure 27. IDRIVE Pin Internal Circuitry

Table 5. IDRIVE Pin Configuration Settings

Source Current

IDRIVE Resistance

IDRIVE Voltage

HS OCP Monitor

<1 k

Ω to GND

GND

6 mA

12.5 mA

ON

33 k

Ω ±5% to GND

0.7 V ±5%

12.5 mA

25 mA

ON

200 k

Ω ±5% to GND

2 V ±5%

25 mA

50 mA

ON

>500 k

Ω to GND, High-Z

3 V ±5%

100 mA

200 mA

ON

68 k

Ω ±5% to AVDD

4 V ±5%

150 mA

300 mA

ON

<1 k

Ω to AVDD

AVDD

25 mA

50 mA

OFF

Table 6. IDRIVE Pin Resistor Settings

33 k

Ω ±5% to GND

<1 k

Ω to GND

>500 k

Ω to GND, High-Z

68 k

Ω ±5% to AVDD

<1 k

Ω to AVDD

200 k

Ω ±5% to GND

IDRIVE

IDRIVE

IDRIVE

IDRIVE

IDRIVE

12.5 / 25 mA (33 k

Ω)

25 / 50 mA

6 / 12.5 mA

100 / 200 mA

150 / 300 mA

25 / 50 mA (200 k

Ω)

HS OCP monitor off

20

Submit Documentation Feedback

Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701