DRV8701

SLVSCX5B – MARCH 2015 – REVISED JULY 2015

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Common Pins (continued)

PIN

TYPE

DESCRIPTION

NAME

NO.

Controls the current regulation; apply a voltage between 0.3 V and

VREF

6

Input

Analog reference input

AVDD

Open

Pulled logic low with fault condition; open-drain output requires an

nFAULT

9

Fault indication pin

Drain

external pullup

Open

Pulled logic low when the drive current hits the current chopping

SNSOUT

10

Sense comparator output

Drain

threshold; open-drain output requires an external pullup

SO

11

Output

Shunt amplifier output

offset; place no more than 1 nF of capacitance on this pin

SN

20

Input

Shunt amplifier negative input

Connect to SP through current sense resistor and to GND

Connect to low-side FET source and to SN through current sense

SP

21

Input

Shunt amplifier positive input

resistor

GH1

17

Output

High-side gate

Connect to high-side FET gate

GH2

24

GL1

19

Output

Low-side gate

Connect to low-side FET gate

GL2

22

SH1

18

Input

Phase node

Connect to high-side FET source and low-side FET drain

SH2

23

External Passive Components

COMPONENT

PIN 1

PIN 2

RECOMMENDED

VM

GND

0.1-µF ceramic capacitor rated for VM

VM

GND

≥10-µF capacitor rated for VM

VCP

VM

16-V, 1-µF ceramic capacitor

CPH

CPL

0.1-µF X7R capacitor rated for VM

DVDD

GND

6.3-V, 1-µF ceramic capacitor

AVDD

GND

6.3-V, 1-µF ceramic capacitor

IDRIVE

GND

See Typical Applications for resistor sizing

nFAULT

≥10-kΩ pullup

SNSOUT

≥10-kΩ pullup

SP

SN/GND

Optional low-side sense resistor

(1)

VCC is not a pin on the DRV8701, but a VCC supply voltage pullup is required for open-drain outputs nFAULT and SNSOUT. The

system controller supply can be used for this pullup voltage, or these pins can be pulled up to either AVDD or DVDD.

External FETs

Component

Gate

Drain

Source

Recommended

GH1

VM

SH1

GL1

SH1

SP or GND

Supports up to 200-nC FETs at 40-kHz PWM; see

Detailed Design Procedure for more details

GH2

VM

SH2

GL2

SH2

SP or GND

4

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