TAS5731MPHPR datasheet(26/81 Pages) TI1

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TAS5731M

SLOS838C – JULY 2013 – REVISED AUGUST 2015

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Feature Description (continued)

9.3.7 PWM Section

The TAS5731M DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high

power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to

increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP

and outputs two BTL PWM audio output channels.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can

be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

For a detailed description of using audio processing features like DRC and EQ, see the TAS5731 EVM User's

Guide (SLOU331) and TAS570X GDE Software Setup development tool documentation (SLOC124).

9.3.8 2.1-Mode Support

The TAS5731 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation.

To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must

be set to 1. The SSTIMER pin must be left floating in this mode.

9.3.9 I2C Compatible Serial Control Interface

The TAS5731M DAP has an I2C serial control slave interface to receive commands from a system controller. The

serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait

states. As an added feature, this interface operates even if MCLK is absent. The serial control interface supports

both single-byte and multiple-byte read and write operations for status registers and the general control registers

associated with the PWM.

9.3.10 Audio Serial Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5731M DAP accepts serial data

in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

9.3.10.1 I2S Timing

I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or

64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes

state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit

clock. The DAP masks unused trailing data bit positions.

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