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TAS5731MPHPR 数据表(PDF) 41 Page - Texas Instruments |
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TAS5731MPHPR 数据表(HTML) 41 Page - Texas Instruments |
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41 / 81 page  TAS5731M www.ti.com SLOS838C – JULY 2013 – REVISED AUGUST 2015 9.6 Register Maps Table 3. Serial Control Interface Register Summary NO. OF SUBADDRESS REGISTER NAME CONTENTS(1) INITIALIZATION VALUE BYTES 0x00 Clock control register 1 Description shown in subsequent section 0x6C 0x01 Device ID register 1 Description shown in subsequent section 0x00 0x02 Error status register 1 Description shown in subsequent section 0x00 0x03 System control register 1 1 Description shown in subsequent section 0xA0 0x04 Serial data interface 1 Description shown in subsequent section 0x05 register 0x05 System control register 2 1 Description shown in subsequent section 0x40 0x06 Soft mute register 1 Description shown in subsequent section 0x00 0x07 Master volume 1 Description shown in subsequent section 0xFF (mute) 0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x0A Channel 3 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x0B–0x0D 1 Reserved(2) 0x0E Volume configuration 1 Description shown in subsequent section 0x91 register 0x0F 1 Reserved(2) 0x10 Modulation limit register 1 Description shown in subsequent section 0x02 0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC 0x12 IC delay channel 2 1 Description shown in subsequent section 0x54 0x13 IC delay channel 3 1 Description shown in subsequent section 0xAC 0x14 IC delay channel 4 1 Description shown in subsequent section 0x54 0x15-0x18 1 Reserved(2) 0x19 PWM channel shutdown 1 Description shown in subsequent section 0x30 group register 0x1A Start/stop period register 1 0x0F 0x1B Oscillator trim register 1 0x82 0x1C BKND_ERR register 1 0x02 0x1D–0x1F 1 Reserved(2) 0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772 0x21 Ch 4 source select register 4 Description shown in subsequent section 0x0000 4303 0x22 -0x24 4 Reserved(2) 0x25 PWM MUX register 4 Description shown in subsequent section 0x0102 1345 0x26-0x28 4 Reserved(2) 0x29 ch1_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x2A ch1_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 (1) A u indicates unused bits. (2) Reserved registers must not be accessed. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 41 Product Folder Links: TAS5731M |
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