TAS5731MPHPR datasheet(36/81 Pages) TI1

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TAS5731M

SLOS838C – JULY 2013 – REVISED AUGUST 2015

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Device Functional Modes (continued)

Figure 59. 2.1 Mode

Refer to 2.1 Application section for more details of the correct 2.1 output connection of the TAS5731M.

9.5 Programming

9.5.1 I2C Serial Control Interface

The TAS5731M DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and

supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.

This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The

control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation

(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.

9.5.1.1 General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A

high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit

transitions must occur within the low time of the clock period. These conditions are shown in Figure 60. The

master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS5731M holds SDA low during the acknowledge

clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the

sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible

devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor

must be used for the SDA and SCL signals to set the high level for the bus.

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