TAS5731MPHPR datasheet(37/81 Pages) TI1

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7-BitSlave Address

8-BitRegister Address(N)

8-BitRegisterDataFor

Address(N)

Start

Stop

SDA

SCL

8-BitRegisterDataFor

Address(N)

T0035-01

TAS5731M

www.ti.com

SLOS838C – JULY 2013 – REVISED AUGUST 2015

Programming (continued)

Figure 60. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in Figure 60.

The 7-bit address for TAS5731M is 0011 011 (0x36).

9.5.1.2 Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses

0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-

byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress

assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does

not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes

that are required for each specific subaddress. For example, if a write command is received for a biquad

subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received

when a stop command (or another start command) is received, the received data is discarded.

Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The

TAS5731M also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by

data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place,

and the data for all 16 subaddresses is successfully received by the TAS5731M. For I2C sequential-write

transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted,

before a stop or start is transmitted, determines how many subaddresses are written. As was true for random

addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data

is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is

accepted; only the incomplete data is discarded.

9.5.1.3 Single-Byte Write

As shown in Figure 61, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I2C device address

and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or

bytes corresponding to the TAS5731M internal memory address being accessed. After receiving the address

byte, the TAS5731M again responds with an acknowledge bit. Next, the master device transmits the data byte to

be written to the memory address being accessed. After receiving the data byte, the TAS5731M again responds

with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-

write transfer.

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