数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

TAS5731MPHPR 数据表(PDF) 10 Page - Texas Instruments

Click here to check the latest version.
部件名 TAS5731MPHPR
功能描述  Digital Audio Power Amplifier
PDF  81 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TAS5731MPHPR 数据表(HTML) 10 Page - Texas Instruments

Back Button TAS5731MPHPR Datasheet HTML 6Page - Texas Instruments TAS5731MPHPR Datasheet HTML 7Page - Texas Instruments TAS5731MPHPR Datasheet HTML 8Page - Texas Instruments TAS5731MPHPR Datasheet HTML 9Page - Texas Instruments TAS5731MPHPR Datasheet HTML 10Page - Texas Instruments TAS5731MPHPR Datasheet HTML 11Page - Texas Instruments TAS5731MPHPR Datasheet HTML 12Page - Texas Instruments TAS5731MPHPR Datasheet HTML 13Page - Texas Instruments TAS5731MPHPR Datasheet HTML 14Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 81 page
background image
TAS5731M
SLOS838C – JULY 2013 – REVISED AUGUST 2015
www.ti.com
7.10 Timing Requirements - PLL Input Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fMCLKI
MCLK frequency
2.8224
24.576
MHz
MCLK duty cycle
40%
50%
60%
tr/tf(MCLK)
Rise/fall time for MCLK
5
ns
LRCLK allowable drift before LRCLK reset
4
MCLKs
7.11 Timing Requirements - Serial Audio Ports Slave Mode
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
CL = 30 pF
1.024
12.288
MHz
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCLK frequency
8
48
48
kHz
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK rising edges between LRCLK rising
SCLK
32
64
edges
edges
LRCLK clock edge with respect to the falling
SCLK
t(edge)
–1/4
1/4
edge of SCLK
period
tr/tf
Rise/fall time for SCLK/LRCLK
8
ns
7.12 Timing Requirements - I
2C Serial Control Port Operation
for I
2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
fSCL
Frequency, SCL
No wait states
400
kHz
tw(H)
Pulse duration, SCL high
0.6
μs
tw(L)
Pulse duration, SCL low
1.3
μs
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
0
ns
t(buf)
Bus free time between stop and start conditions
1.3
μs
tsu2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
μs
7.13 Timing Requirements - Reset (RESET)
control signal parameters over recommended operating conditions (unless otherwise noted).
PARAMETER
MIN
TYP
MAX
UNIT
tw(RESET)
Pulse duration, RESET active
100
μs
td(I2C_ready)
Time to enable I2C
12
ms
10
Submit Documentation Feedback
Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: TAS5731M



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com