MEC1322 datasheet(39/456 Pages) MICROCHIP

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DS00001719D-page 39

MEC1322

1.6

Notes for Tables in this Chapter

1.7

Pin States After VCC1 Power-On

Pins that default to IOD or OD in the Multiplexing Tables are open drain and come up tri-stated after VCC1 power-on.

Pins that default to I are inputs and also come up tri-stated (high-z).

Table 1-40 shows pins that have specific states after VCC1 power-on.

Note 1

The LAD and SER_IRQ pins require an external weak pull-up resistor of 10k-100k ohms.

Note 2

When the JTAG_RST# pin is not asserted (logic '1'), the JTAG_TDI, JTAG_TDO, JTAG_TCK, JTAG_TMS

signal functions in the JTAG interface are unconditionally routed to the interface; the Pin Control register for

these pins has no effect. When the JTAG_RST# pin is asserted (logic '0'), the JTAG_TDI, JTAG_TDO,

JTAG_TCK, JTAG_TMS signal functions in the JTAG interface are not routed to the interface and the Pin

Control Register for these pins controls the muxing. The pin control registers can not be used to route the

JTAG interface to the pins. The System Board Designer should terminate this pin in all functional states

using jumpers and pull-up or pull down resistors, etc.

Note 3

An external cap must be connected as close to the CAP pin/ball as possible with a routing resistance and

CAP ESR of less than 100mohms. The capacitor value is 1uF and must be ceramic with X5R or X7R

dielectric. The cap pin/ball should remain on the top layer of the PCB and traced to the CAP. Avoid adding

vias to other layers to minimize inductance.

Note 4

A pull-down is required on the GPIO146/PVT_CS0# pin if there is no private SPI flash device on the board.

Note 5

This I2C port supports 1Mbps (pin 88, GPIO023/I2C1_DAT0 and pin 89, GPIO022/I2C1_CLK0). For 1Mbps

I2C recommended capacitance/pull-up relationships from Intel, refer to the Shark Bay platform guide, Intel

ref number 486714. Refer to the PCH - SMBus 2.0/SMLink Interface Design Guidelines, Table 20-5 Bus

Capacitance/Pull-Up Resistor Relationship.

Note 6

The following glitch protected pins require a pull-down on the board: pin 60, nRESET_OUT/GPIO121 and

pin 85, GPIO143/RSMRST#. The nRESET_OUT pin will drive low when VCC1 comes on and stays low

until the iRESET_OUT bit is cleared after VCC PWRGD asserts. The RSMRST# pin also drives low (as a

GPIO push-pull output) following a VCC1 power-on until firmware deasserts it by writing the GPIO data bit

to '1'. The GPIO143/RSMRST# pin operates in this manner as a GPIO; the RSMRST# function is not a true

alternate function and the GPIO143 control register must not be changed from the GPIO default function.

Note 7

The BC DAT pin requires a weak pull up resistor (100 K Ohms).

Note 8

The voltage on the ADC pins must not exceed 3.6 V or damage to the device will occur.

Note 9

The XTAL1 pin should be left floating when using the XTAL2 pin for the single ended clock input.

Note 10

MEC1322: The SPI pins are configured to their SPI function by ROM boot code as follows. Shared SPI

pins are configured to the following SPI functions: SHD_CLK, SHD_MOSI, SHD_MISO and SHD_CS0#. If

the PVT_CS0# pin (pin 96) is sampled high, then the private SPI pins are configured to the following SPI

functions after a successful load from flash: PVT_CLK, PVT_MOSI, PVT_MISO and PVT_CS0#; otherwise

these pins are left as the GPIO function. It is recommended that user code reconfigures the shared SPI

pins to the GPIO input function before releasing RSMRST#.

Note 11

The KSI[7:0] pins have the internal pull-up enabled by ROM boot code. Therefore the Buffer Type on these

pins is I (PU) after the ROM boot code runs.

Note 12

The GPIO041 pin defaults to output low. This pin must be reprogrammed to the GPIO function upon power-

up.

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