MEC1322 datasheet(91/456 Pages) MICROCHIP

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DS00001719D-page 91

MEC1322

5.9.3

I/O BASE ADDRESS REGISTERS (BARS)

The LPC Controller has implemented a Base Address Register (BAR) for each Logical Device in the LPC Configuration

space.

• For a description of the Base Address Register format see Section 5.9.3.1, "I/O Base Address Register Format,"

on page 91.

• For a description of the BARs per Logical Device see Table 5-16, “I/O Base Address Registers,” on page 92.

On every LPC bus I/O access the unmasked portion of the programmed LPC Host Address in each of the Base Address

Registers are checked in parallel and if any matches the LPC I/O address the LPC Controller claims the bus cycle.

The format of each BAR is summarized in Section 5.9.3.1, "I/O Base Address Register Format," on page 91.

5.9.3.1

I/O Base Address Register Format

Each LPC accessible logical device has a programmable Base Address Register. The following table defines the

generic format used for all of these registers. See Table 5-16, "I/O Base Address Registers" for a list of all the Logical

Device Base Address registers implemented.

Note 5-10

Offset 60h is the LPC Base Address register. The LPC Base Address register is only reset on

VCC1_RESET. However, bits[31:16] are reloaded on nSIO_RESET with the value in the LPC BAR

Init Register.

Note 5-11

Bits[31:16] LPC Host Address bit field in the LPC Base Address register at offset 60h must be written

LSB then MSB. This particular register has a shadow that lets the Host come in and write to the lower

byte of the 16-bit address, and the resulting 16-bit LPC Host address field does not update. Writing

to the upper byte triggers a full 16-bit field update.

Note:

Software should that insure that no two BARs map the same LPC I/O address. If two BARs do map to the

same address, the LPC_INTERNAL_ERR and BAR_CONFLICT status bits are set when an LPC access

is targeting the address with the BAR conflict.

Offset

See Table 5-16, “I/O Base Address Registers,” on page 92

Bits

Description

Type

Default

Reset

Event

31:16 LPC Host Address

These 16 bits are used to match LPC I/O addresses

R/W

(Note 5-

11)

See

Table 5-16

Note 5-

15 VALID

If this bit is 1, the BAR is valid and will participate in LPC matches. If

it is 0 this BAR is ignored

R/W

See

Table 5-16

Note 5-

14 DEVICE (device)

This bit combined with FRAME constitute the Logical Device Num-

ber. DEVICE identifies the physical location of the logical device.

This bit should always be set to 0.

See

Table 5-16

Note 5-

13:8 FRAME

These 6 bits are used to specify a logical device frame number

within a bus. This field is multiplied by 400h to provide the frame

address within the peripheral bus address. Frame values for frames

corresponding to logical devices that are not present on the device

are invalid.

See

Table 5-16

Note 5-

7:0 MASK

These 8 bits are used to mask off address bits in the address match

between an LPC I/O address and the Host Address field of the

BARs, as described in Section 5.8.2.1, "I/O Transactions". A block of

up to 256 8-bit registers can be assigned to one base address.

See

Table 5-16

Note 5-

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