 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
MEC1322 数据表(PDF) 92 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MEC1322 数据表(HTML) 92 Page - Microchip Technology |
|
|
92 / 456 page  MEC1322 DS00001719D-page 92 2014 - 2015 Microchip Technology Inc. 5.9.3.2 Logical Device I/O BAR Description The following table defines the LPC I/O BAR of each logical device implemented in the design. TABLE 5-16: I/O BASE ADDRESS REGISTERS 5.9.4 DEVICE MEMORY BASE ADDRESS REGISTERS Some Logical Devices have a Memory Base Address Register. These Device Memory BARs are located in blocks of Configuration Registers in Logical Device 0Ch, in the AHB address range 400F_33C0h through 400F_33FFh. The fol- lowing table defines the generic format used for all of these registers. Each Device Memory BAR is 48 bits wide. The format of each Device Memory BAR is summarized in Device Memory Base Address Register Format. An LPC memory request is translated by the Device Memory BAR into an 8-bit read or write transaction on the AHB bus. The 32-bit LPC memory address is translated into a 24-bit AHB address 5.9.4.1 Device Memory Base Address Register Format Offset See Table 5-17, "Device Memory Base Address Register Default Values" Bits Description Type Default Reset Event 47:16 HOST_ADDRESS[31:0] These 32 bits are used to match LPC memory addresses. R/W See Table 5-17 nSIO_R ESET 15 VALID If this bit is 1, the BAR is valid and will participate in LPC matches. If it is 0 this BAR is ignored. R/W See Table 5-17 nSIO_R ESET 14 RESERVED RES - - Bits [D31:D16] Bit [D15] Bit [D14] Bits [D13:D8] Bits [D6:D0] Offset Logical Device Number Logical Devices Reset Default Default LPC I/O Host Address VALID DEVICE FRAME MASK 60h C LPC Interface (Configuration Port) 002E_0C01 (Note 1) 002E 0 0 C 1 64h 0 EMI 0 0000_000F 0000 0 0 0 F 68h 7 UART 0 0000_0707 0000 0 0 7 7 78h 1 8042EM 0060_0104 0060 0 0 1 4 88h 3 ACPI EC0 0062_0304 0062 0 0 3 4 8Ch 4 ACPI EC1 0066_0407 0066 0 0 4 7 90h 5 ACPI PM1 0000_0507 0000 0 0 5 7 94h 6 Legacy Port92/GateA20 0092_0600 0092 0 0 6 0 98h 9 Mailbox 0000_0901 0000 0 0 9 1 9Ch B RTC 0000_0B3F 0000 0 0 B 3F Base Address Register Bit Field Descriptions Note 2: The FRAME and MASK fields for these Legacy devices are not used to determine which LPC I/O addresses to claim. The address range match is maintained within the blocks themselves. Note 1: The default Base I/O Address of the Configuration Port can be relocated by programming the BAR register for Logical Device Ch (LPC/Configuration Port) at offset 60h. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
