MEC1322 datasheet(72/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 72

 2014 - 2015 Microchip Technology Inc.

4.0

VBAT REGISTER BANK

4.1

Introduction

This chapter defines a bank of registers powered by VBAT.

4.2

Interface

This block is designed to be accessed internally by the EC via the register interface.

4.3

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

4.3.1

POWER DOMAINS

4.3.2

CLOCK INPUTS

This block does not require any special clock inputs. All register accesses are synchronized to the host clock.

4.3.3

RESETS

4.4

Interrupts

4.5

Low Power Modes

The VBAT Register Bank is designed to always operate in the lowest power consumption state.

4.6

Description

The VBAT Register Bank block is a block implemented for aggregating miscellaneous battery-backed registers required

the host and by the Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC sub-

system.

4.7

EC-Only Registers

Note 4-1

The Base Address indicates where the first register can be accessed in a particular address space

for a block instance.

TABLE 4-1:

POWER SOURCES

Name

Description

VBAT

The VBAT Register Bank are all implemented on this single power

domain.

TABLE 4-2:

RESET SIGNALS

Name

Description

VBAT_POR

This reset signal, which is an input to this block, resets all the logic and

registers to their initial default state.

TABLE 4-3:

INTERRUPT SIGNALS

Name

Description

PFR_Status

This interrupt signal from the Power-Fail and Reset Status Register

indicates VBAT RST and WDT events.

TABLE 4-4:

EC-ONLY REGISTER BASE ADDRESS TABLE

Block Instance

Instance

Number

Host

Address Space

Base Address (Note 4-1)

VBAT_REG_BANK

32-bit internal

address space

4000A400h

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