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MEC1322 数据表(PDF) 65 Page - Microchip Technology |
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MEC1322 数据表(HTML) 65 Page - Microchip Technology |
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65 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 65 MEC1322 3.9.11 SLOW CLOCK CONTROL REGISTER (SLOW_CLK_CNTRL) 3.9.12 OSCILLATOR ID REGISTER (CHIP_OSC_ID) 6 PS2_1 Clock Required 0: block does NOT need clocks. 1: block requires clocks. R0h VCC1_R ESET 5 PS2_0 Clock Required 0: block does NOT need clocks. 1: block requires clocks. R0h VCC1_R ESET 4 MCHP Reserved R0h VCC1_R ESET 3 ADC Clock Required 0: block does NOT need clocks. 1: block requires clocks. R0h VCC1_R ESET 2:0 RESERVED RES Offset 2Ch Bits Description Type Default Reset Event 31:10 RESERVED RES 9:0 Slow Clock (100 kHz) Divide Value Configures the 100kHz_Clk. 0: Clock off n: divide by n. Note: The default setting is for 100 kHz. R/W 1E0h VCC1_R ESET Offset 30h Bits Description Type Default Reset Event 31:9 RESERVED RES 8OSC_LOCK Oscillator Lock Status R0h VCC1_R ESET 7:0 MCHP Reserved R N/A VCC1_R ESET Offset 28h Bits Description Type Default Reset Event |
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