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MEC1322 数据表(PDF) 73 Page - Microchip Technology |
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MEC1322 数据表(HTML) 73 Page - Microchip Technology |
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73 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 73 MEC1322 4.7.1 POWER-FAIL AND RESET STATUS REGISTER The Power-Fail and Reset Status Register collects and retains the VBAT RST and WDT event status when VCC1 is unpowered. 4.7.2 CLOCK ENABLE REGISTER APPLICATION NOTE: The XOSEL bit should be correctly configured by firmware before the 32K_EN bit is assserted. TABLE 4-5: RUNTIME REGISTER SUMMARY Offset Register Name 00h Power-Fail and Reset Status Register 04h MCHP Reserved 08h Clock Enable Register Address 00h Bits Description Type Default Reset Event 7 VBAT_RST The VBAT RST bit is set to ‘1’ by hardware when a VBAT_POR is detected. This is the register default value. To clear VBAT RST EC firmware must write a ‘1’ to this bit; writing a ‘0’ to VBAT RST has no affect. R/WC 1 VBAT_P OR 6 Reserved RES - - 5 WDT The WDT bit is asserted (‘1’) following a Watch-Dog Timer Forced Reset (WDT Event). To clear the WDT bit EC firmware must write a ‘1’ to this bit; writing a ‘0’ to the WDT bit has no affect. R/WC 0 VBAT_P OR 4:1 Reserved RES - - 0 DET32K_IN 0 = No clock detected on the XTAL[1:2] pins. 1= Clock detected on the XTAL[1:2] pins. RX VBAT_P OR Address 08h Bits Description Type Default Reset Event 31:2 RESERVED RES - - 1 32K_EN This bit controls the 32.768 KHz Crystal Oscillator as defined in TABLE 4-6:. R/W 0b VBAT_P OR 0 XOSEL This bit controls whether a crystal or single ended clock source is used. 1= the 32.768 KHz Crystal Oscillator is driven by a single-ended 32.768 KHz clock source connected to the XTAL2 pin. 0= the 32.768 KHz Crystal Oscillator requires a 32.768 KHz parallel resonant crystal connected between the XTAL1 and XTAL2 pins (default). R/W 0b VBAT_P OR |
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