L9663 datasheet(52/104 Pages) STMICROELECTRONICS

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Communication interface

L9663

52/104

DocID028693 Rev 1

SR2

Status Register 2

Address:

000101

Type:

RC (latched and cleared on read, except if otherwise specified)

Description:

[11] OTP_CRC_ERR: Error from OTP trimming bits [realtime]

[10] VAS_UV: Under voltage detected on VAS. Latched bit

[9] VAS_OV: Over voltage detected on VAS [realtime]

[8] VAS_UVL: Under voltage detected on VAS. When below VVASU_off, VAS is switched off.

Latched bit. Cleared upon VAS_EN=’0’ confirmation from MCU

[7] SYNC2_TOUT: Exceeded tw timeout of 100 μs on SYNC2 pin during sync pulse (sync pulse

driven by pin source)

[6] UDB2_FLT: Write operation on Upstream Data Buffer 2 occurred while buffer is busy (i.e.

UDB2_BUSY=1)

[5] SYNC2_SLOW: No SYNC pulse generated, delayed SYNC pulse or SYNC voltage <

2.5V/3.5V on PSI5 interface 2

[4] SYNC2_UV: SYNC pulse < 2.5V/3.5V for a time longer than specified on PSI5 interface 2

[3] SYNC1_TOUT: Exceeded tw timeout of 100 μs on SYNC1 pin during sync pulse (sync pulse

driven by pin source)

[2] UDB1_FLT: Write operation on Upstream Data Buffer 1 occurred while buffer is not empty (i.e.

UDB1_BUSY=1)

[1] SYNC1_SLOW: No SYNC pulse generated, delayed SYNC pulse or SYNC voltage < 2.5V/3.5V

on PSI5 interface 1

[0] SYNC1_UV: SYNC pulse < 2.5V/3.5V for a time longer than specified on PSI5 interface 1

Default value:

----------------

[15] XCT2_R(1): Result of cross-coupling test on PSI5 interface 2

[14] BE2: Buffer empty fault on PSI5 interface 2

[13] OL2: Open load on PSI5 interface 2

[12] STB2Short to VBAT on PSI5 interface 2

Masked towards FSR2 status bit during cross coupling test

[11] LKG2: Leakage to GND on PSI5 interface 2

L9663 数据表(PDF) 52 Page - STMicroelectronics

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