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L9663 数据表(PDF) 98 Page - STMicroelectronics |
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L9663 数据表(HTML) 98 Page - STMicroelectronics |
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98 / 104 page  Errata L9663 98/104 DocID028693 Rev 1 7 Errata – Ch 1, slot 6 – Ch 2, slot 6 – Ch 1, slot 5 – Ch 2, slot 5 –… – Ch 2, slot 1 – Ch 1, slot 1 – Ch 2, slot 1 –1μs ≤ tw ≤ 5μs ≥ a short pulse is generated, PSI5 standard compliant; ≥ Correct short pulse – tw > 5μs ≥ the pulse could be not compliant with PSI5 standard, two consecutive pulses could be generated instead of a single pulse. ≥ Wrong pulse Table 27. Errata BugID# Component Revision Category / Function Issue Description 1526 L9663BA Asynchronous Mode FIFO_LOCK could still stay set even after clearing of the data buffer registers of the 2 PSI5 channels. Assuming a low data rate from sensor compared to SPI readout, the proposed workaround is to read both FIFOs in the following sequence: Afterwards, if the FIFO_LOCK bit is still high, the following read commands are needed: 1822 L9663BA Sync Pulse If the IC is configured to control the sync pulse length via pin (PSIx_EXT_UDB=0 and PSIx_TRIG_SEL=00/11, x=1 or 2) the generated sync pulse could be not compliant with the PSI5 standard, depending on the trigger pulse duration tw. 1830 L9663BA Cross coupling test XCTRSLT1/2 fault flags are swapped in master mode 3367 L9663BA Clock monitor by internal oscillator The internal clock monitor (disabled by default) is not accurate enough: fCLKERR_H/L thresholds overlap the main oscillator operating range. This function is disabled by default, it can be enabled by ST only (burning a dedicated OTP bit). If enabled it could detect false errors. => Activation is forbidden. |
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