L9663 datasheet(45/104 Pages) STMICROELECTRONICS

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L9663

Diagnosis

103

If the VAS voltage is lower than the under voltage threshold for longer than the filter time, the

SPI bit VAS_UV in SR1 reg is set to '1' and it is latched and cleared upon read.

If the VAS voltage is higher than the over voltage threshold for longer than the filter time, the

SPI bit VAS_OV in SR1 reg is set to '1' (NOT latched). In addition to that, in case of further

lower under voltage condition (VVASU_off), VAS is switched off to protect the external n-

channel FET component from high current flow when external pin is shorted to ground. The

fault bit VAS_UVL (SR1) is latched and gets cleared only when a SPI switch off command

for confirmation is sent. The current status (on/off) can be read via SPI (SR3).

The regulator can be switched on again by switching off and on via SPI.

When POR is de-asserted, under voltage is masked for the time needed by soft start circuit

to switch on the regulator (1 ms).

During reset, the under/over voltage bits are set to 0.

4.6

Monitoring of Synchronous Pulse amplitude

To detect possible communication problems due to sync pulses which do not conform to the

standard, this module monitors the parameters of the sync pulse and registers any deviation

from the standard.

Basic features:



Comparator



Evaluation block



Flag readable via SPI

Figure 25. Timing for sync pulse voltage monitoring

L9663 数据表(PDF) 45 Page - STMicroelectronics