L9663 datasheet(37/104 Pages) STMICROELECTRONICS

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L9663

Satellite interface

103



Triggering via SYNCx pins with upstream data buffer. When the SYNCx pin is

triggered, the sync pulse trigger generator internally generates the appropriate sync

pulses, depending on the value in the upstream data buffer.



Triggering via trigger pulse timer: the transceiver IC automatically generates the sync

pulses at fixed time intervals, depending on the value in the upstream data buffer.

The default configuration at startup is to use the triggering via SYNCx pins without upstream

data buffer.

If the triggering with upstream data buffer is used and there aren't data to be sent to the

sensor, a short pulse is sent.

The switch matrix is configurable by an SPI command. It determines whether the sync

pulses are triggered via SPI by the trigger generator (transceiver IC in mode 1) or by the

external trigger pins (transceiver IC in mode 2).

If the trigger pulse timer is used to generate the sync pulse trigger, the interval between two

pulses on interface x is configured by the SPI register SYNC Pulse Timer (SPT). It's

possible also to program the delay between interface 1 and interface 2 sync pulses through

the SYNC_DELAY_PSI1_PSI2 bits in ADVSET2 register. In case the sync pulse trigger

comes from SPI commands or SYNCx pins, the programmed pulse timer still has the

functionality of a filtering time with respect to those triggering commands.

If full flexibility for the sync pulse interval is required, use direct triggering either via SPI or

direct interface.

3.6

Synchronous pulse generator

The Synchronous Pulse Generator is designed to generate synchronous pulses conform to

PSI5 rev. 1.3 (min Vt2 = 3.5 V) as well PSI5 rev. 2.x (min Vt2 = 2.5 V).

The sync pulse is granted according to PSI5 standard with the Ibase current range up to

35 mA.

If the pulse trigger generation is configured with an external trigger and without the

upstream data buffer, the external source must manage the encoding via SPI CHCNT

concerns the duration of the sync pulse (i.e. ECU to sensor communication), otherwise the

IC manages the encoding (tooth gap or pulse width methods, specified in register GCR1, bit

PSIx_TGAP_PW).

An automatic hardware based slew rate control (SRC) ensures PSI5 compliant slew rates

for the rising and falling edge of the sync pulse for an overall capacitive bus load of 15 to

107 nF. The Sync Pulse is shaped like raised cosine instead of trapezoidal to reduce EMC

emission.

During the duration of the sync pulse, the corresponding PSI5 receiver is frozen to avoid

erroneous data detection.

VDD, VAS and VB and other supply voltages are protected against reverse feeding from the

sync pulse.

The pulse length at PSIx will be generated using the Sync Pulse Trigger Generator.

In case of trigger by pin without UDB, the Sync Pulse Generator starts the sync pulse with

the positive edge of the trigger signal, after SYNCx pin filter. The duration of the sync pulse

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