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L9663 数据表(PDF) 46 Page - STMicroelectronics |
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L9663 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 104 page  Diagnosis L9663 46/104 DocID028693 Rev 1 The sync pulses(i) are monitored for under voltage, duration and rising edge transient speed. The circuit evaluates the output voltage versus internal sync trigger signal and sets the corresponding bit(s) in Status Register 1 (SR1): Bit SYNCx_SLOW if a delayed sync pulse or pulse with Vt2< 2.5V /3.5V was generated (slow Vsync rising time) Bit SYNCx_UV if the sync pulse amplitude goes below 2.5V/3.5V for a time longer than the specified filtering time (spec parameter tAsync_V). STB is detected by the over voltage monitoring (see Section 4.4). i. For sync pulse triggering via pin see errata n.1822, Section 7: Errata |
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