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VS6663CD 数据表(PDF) 61 Page - STMicroelectronics |
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VS6663CD 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 64 page  Doc ID027033 Rev 2 61/64 VS6663CD Application 61 11 Application 11.1 Schematic Figure 25. Mobile camera application VS6663CD 1.8V EXTCLK DATA+ CLK- GND SCL SDA 1.8V External clock Power down signal 100R 100R 4.7k XSHUTDOWN DATA- CLK+ SubLVDS data SubLVDS clock CCI control lines VDIG 3.6V . 2.8V VANA VCAP Notes: No connection should be made to VCAP. CCCP2 100R termination may be internal to subLVDS receiver. For CSI-2, the receiver is mandated to have an internal termination which is dynamically switched in and out depending on whether the link is in HIGH SPEED or LOW POWER mode. This transition occurs every line. 220nF . 220nF VCORE CHARGE PUMP 470nF |
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