VS6663CD datasheet(42/64 Pages) STMICROELECTRONICS

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Video timing

VS6663CD

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Doc ID027033 Rev 2

6.2

Video timing

This section specifies the timing for the image data that is readout from the pixel array and

the output image data. These are not necessarily the same size.

The application of all of the video timing read/write parameters must be re-timed to the start

of frame boundary to ensure that the parameters are consistent within a frame. The video

stream which is output from the VS6663CD contains both video data and other auxiliary

information.

6.2.1

PLL block

The VS6663CD contains a phase locked loop (PLL) block, which generates all the

necessary internal clocks from the external clock input. Changes to the PLL settings on the

VS6663CD will only be consumed on the software standby to streaming mode transition.

Figure 16 shows the internal functional blocks, which define the relationship between the

external input clock frequency and the pixel clock frequency.

The majority of the logic within the device is clocked by vt_sys_clk however the CCI block is

clocked by the external input clock.

Figure 16. Clock relationship

The equation relating the input clock frequency to pixel clock frequencies is:

6.2.2

Framerate

The framerate of the array readout and therefore the output framerate is governed by the

line length, frame length and the video timing pixel clock frequency.

•

line length is specified as a number of pixel clocks, line_length_pck

•

frame length is specified as a number of lines, frame_length_lines

•

video timing pixel clock is specified in MHz, vt_pix_clk_freq_mhz

Max.

800 MHz

Min.

300 MHz

Min.

Max.

133

pll_multiplier

Max.

12 MHz

Min.

6 MHz

pre_pll_

clk_div

Range

1, 2, 4

Max.

27 MHz

Min.

6 MHz

Ext.

input

clock

External input clock

ext_clk_freq_mhz

PLL input clock

pll_ip_clk_freq_mhz

PLL output clock

pll_op_clk_freq_mhz

Video timing pixel clock

vt_pix_clk_freq_mhz

Video timing system clock

vt_sys_clk_freq_mhz

Max.

800 MHz(2)

Min.

75 MHz(1)

Range

1, 2, 4

vt_sys_clk

_div

vt_pix_clk

_div

Max.

80 MHz

Min.

7.5 MHz

Min.

Max.

1. The minimum vt_sys_clk_freq_mhz is 80 MHz in CSI-2 mode.

2. The maximum vt_sys_clk_freq_mhx is 640 MHz in CCP mode.

vt_pix_clk_freq_mhz

ext_clk_freq_mhz

pll_multiplier

pre_pll_clk_div

vt_sys_clk_div

vt_pix_clk_div

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