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VS6663CD 数据表(PDF) 33 Page - STMicroelectronics |
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VS6663CD 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 64 page  Doc ID027033 Rev 2 33/64 VS6663CD Camera control interface (CCI) 47 0x111C Hi max_pll_op_freq_mhz 32SF 44.48 00.00 RO Maximum PLL output clock frequency Units: MHz Value: 800.0 0x111D 3rd 0x111E 2nd 0x111F Lo 0x1120 Hi min_vt_sys_clk_div 16UI 00.01 RO Minimum video-timing system clock divider value Value: 1 0x1121 Lo 0x1122 Hi max_vt_sys_clk_div 16UI 00.04 RO Maximum video-timing system clock divider value Value: 4 0x1123 Lo 0x1124 Hi min_vt_sys_clk_freq_mhz 32SF 42.96 00.00 RO Minimum video-timing system clock frequency Units: MHz Value: 75.0 This value is 80 MHz in CSI2 mode. 0x1125 3rd 0x1126 2nd 0x1127 Lo 0x1128 Hi max_vt_sys_clk_freq_mhz 32SF 44.48 00.00 RO Maximum video-timing system clock frequency Units: MHz Value: 800.0 The maximum value is 640 MHz in CCP mode. 0x1129 3rd 0x112A 2nd 0x112B Lo 0x112C Hi min_vt_pix_clk_freq_mhz 32SF 40.F0 00.00 RO Minimum video-timing pixel clock frequency Units: MHz Value: 7.5 0x112D 3rd 0x112E 2nd 0x112F Lo 0x1130 Hi max_vt_pix_clk_freq_mhz 32SF 42.A0 00.00 RO Maximum video-timing pixel clock frequency Units: MHz Value: 80.0 0x1131 3rd 0x1132 2nd 0x1133 Lo 0x1134 Hi min_vt_pix_clk_div 16UI 00.08 RO Minimum video-timing pixel clock divider Value: 8 0x1135 Lo 0x1136 Hi max_vt_pix_clk_div 16UI 00.0A RO Maximum video-timing pixel clock divider Value: 10 0x1137 Lo 0x1140 Hi min_frame_length_lines 16UI 00.D0 RO Minimum frame length allowed. Value = 208 Units: Lines 0x1141 Lo Table 21. Video timing parameter limit registers [0x1100 to 0x11FF] (continued) Index Byte Register name Data type Default Type Comment |
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