VS6663CD datasheet(20/64 Pages) STMICROELECTRONICS

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Functional description

VS6663CD

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Doc ID027033 Rev 2

3.2.3

Internal power-on reset (POR)

The VS6663CD internally performs a power-on reset (POR) when the digital supply rises

through the trigger level, Vtrig_rising. Similarly, if the digital power supply falls through the

trigger level, Vtrig_falling, then the power-on reset will also trigger.

Figure 10. POR timing

POR Cell Output

Digital

Power

Supply,

VDIG

Vtrig_rising

Burst > t2

Vtrig_falling

Burst < t4

Burst > t5

Table 8. POR cell characteristics

Symbol

Constraint

Minimum

Typical

Maximum

Units

VDIG rising crossing Vtrig_rising – Internal reset

being released.

20.7

30.7

50.7

µs

Minimum VDIG spike width below Vtrig_falling

which is considered to be a reset when POR cell

output high.

1.25

2.1

6.9

µs

t3(1)

VDIG falling crossing Vtrig_falling - Internal reset

active.

1.25

2.1

6.9

µs

Minimum VDIG spike width below Vtrig_falling

which is considered to be a reset when POR cell

output low.

1.5

2.1

6.9

µs

Minimum VDIG spike width above Vtrig_rising

which is considered to be a supply is stable when

POR cell output low. While the POR cell output is

low, all VDIG spikes above Vtrig_rising which are

less than t5 must be ignored.

20.7

30.7

50.7

Vtrig_rising

VDIG rising trigger voltage.

429

755

944

Vtrig_falling

VDIG falling trigger voltage.

401

725

904

The device could be reset by any VDIG voltage excursion falling below Vtrig_falling and will always be reset by a VDIG

voltage excursion below Vtrig_falling of > 0.5 µs

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